Unverified Commit e5b3fc12 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!4751 [sync] PR-4623: i2c: Optimized the value setting of maxwrite limit to fifo depth - 1 

Merge Pull Request from: @openeuler-sync-bot 
 

Origin pull request:
 
https://gitee.com/openeuler/kernel/pulls/4623
 
 
The driver finishes a write cycle by read the fifo tx full status
or write limit decrease to 0. The driver starts to write data to
the FIFO after the I2C FIFO almost empty interrupt is reported.
The threshold for FIFO almost empty interrupt is that the amount
of data in the FIFO is less than or equal to 1.
Reduce write maxwrite to the fifo depth - aempty interrupt
threshold. Limiting the number of data to be written at a time
to remaining fifo capacity.

https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git/commit/?h=i2c/i2c-host&id=69dc3880100288972fe341c2c59c40fdecf511f5
commit:5c015726a266b33227bc91a6926b3e93de834117

https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git/commit/?h=i2c/i2c-host&id=2f9af34c79ffd97858649822e1730ead2a31f6c6
commit:9911be1d372946924b1fedaa1b96574920f35519 
 
Link:https://gitee.com/openeuler/kernel/pulls/4751

 

Signed-off-by: default avatarZhang Changzhong <zhangchangzhong@huawei.com>
parents b8504baf aff8d64f

drivers/i2c/busses/i2c-hisi.c

+12 −1
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
#define   HISI_I2C_FS_SPK_LEN_CNT	GENMASK(7, 0)

#define HISI_I2C_HS_SPK_LEN		0x003c

#define   HISI_I2C_HS_SPK_LEN_CNT	GENMASK(7, 0)

#define HISI_I2C_TX_INT_CLR		0x0040

#define   HISI_I2C_TX_AEMPTY_INT		BIT(0)

#define HISI_I2C_INT_MSTAT		0x0044

#define HISI_I2C_INT_CLR		0x0048

#define HISI_I2C_INT_MASK		0x004C
@@ -128,6 +130,11 @@ static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 
	writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);

}



static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask)

{

	writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR);

}



static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr)

{

	u32 int_err = ctlr->xfer_err, reg;
@@ -172,6 +179,7 @@ static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 
	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);



	hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);

	hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);

	hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL);



	return 0;
@@ -270,7 +278,7 @@ static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 


static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr)

{

	int max_write = HISI_I2C_TX_FIFO_DEPTH;

	int max_write = HISI_I2C_TX_FIFO_DEPTH - HISI_I2C_TX_F_AE_THRESH;

	bool need_restart = false, last_msg;

	struct i2c_msg *cur_msg;

	u32 cmd, fifo_state;
@@ -327,6 +335,8 @@ static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 
	 */

	if (ctlr->msg_tx_idx == ctlr->msg_num)

		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY);



	hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);

}



static irqreturn_t hisi_i2c_irq(int irq, void *context)
@@ -367,6 +377,7 @@ static irqreturn_t hisi_i2c_irq(int irq, void *context) 
	if (int_stat & HISI_I2C_INT_TRANS_CPLT) {

		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);

		hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);

		hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);

		complete(ctlr->completion);

	}