Commit aff8d64f authored by Devyn Liu's avatar Devyn Liu Committed by openeuler-sync-bot
Browse files

i2c: hisi: Add clearing tx aempty interrupt operation 

maillist inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I92EM3

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git/commit/?h=i2c/i2c-host&id=2f9af34c79ffd97858649822e1730ead2a31f6c6



-----------------------------------------------------

The driver receives the tx fifo almost empty(aempty) interrupt and
reads the tx_aempty_int_mstat to start a round of data transfer.
The operation of clearing the TX aempty interrupt after completing
a write cycle is added to ensure that the FIFO is truly at almost
empty status when an aempty interrupt is received.
The threshold for fifo almost empty interrupt is defined as 1.

Signed-off-by: default avatarDevyn Liu <liudingyuan@huawei.com>
Reviewed-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@kernel.org>
Signed-off-by: default avatarAndi Shyti <andi.shyti@kernel.org>
(cherry picked from commit 12b08189)
parent 2e5e2919

drivers/i2c/busses/i2c-hisi.c

+11 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
#define   HISI_I2C_FS_SPK_LEN_CNT	GENMASK(7, 0)

#define HISI_I2C_HS_SPK_LEN		0x003c

#define   HISI_I2C_HS_SPK_LEN_CNT	GENMASK(7, 0)

#define HISI_I2C_TX_INT_CLR		0x0040

#define   HISI_I2C_TX_AEMPTY_INT		BIT(0)

#define HISI_I2C_INT_MSTAT		0x0044

#define HISI_I2C_INT_CLR		0x0048

#define HISI_I2C_INT_MASK		0x004C
@@ -128,6 +130,11 @@ static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 
	writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);

}



static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask)

{

	writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR);

}



static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr)

{

	u32 int_err = ctlr->xfer_err, reg;
@@ -172,6 +179,7 @@ static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 
	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);



	hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);

	hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);

	hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL);



	return 0;
@@ -327,6 +335,8 @@ static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 
	 */

	if (ctlr->msg_tx_idx == ctlr->msg_num)

		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY);



	hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);

}



static irqreturn_t hisi_i2c_irq(int irq, void *context)
@@ -367,6 +377,7 @@ static irqreturn_t hisi_i2c_irq(int irq, void *context) 
	if (int_stat & HISI_I2C_INT_TRANS_CPLT) {

		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);

		hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);

		hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);

		complete(ctlr->completion);

	}