Commit e54de91a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-fixes-5.4-2019-10-30' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



drm-fixes-5.4-2019-10-30:

amdgpu:
- clang fixes
- Updated golden settings
- GPUVM fixes for navi
- Navi sdma fix
- Navi display fixes
- Freesync fix
- Gamma fix for DCN
- DP dongle detection fix
- Fix for undervolting on vega10

radeon:
- enable kexec fix for PPC

scheduler:
- set an error on fence if hw job failed

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191030162339.44366-1-alexander.deucher@amd.com
parents 2cac8c44 e8a170ff

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+3 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 
	struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);

	struct dma_fence *fence = NULL, *finished;

	struct amdgpu_job *job;

	int r;

	int r = 0;



	job = to_amdgpu_job(sched_job);

	finished = &job->base.s_fence->finished;
@@ -243,6 +243,8 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 
	job->fence = dma_fence_get(fence);



	amdgpu_job_free_resources(job);



	fence = r ? ERR_PTR(r) : fence;

	return fence;

}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+3 −3
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] = 
{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
@@ -140,7 +140,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
@@ -179,7 +179,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

+9 −0
Original line number Diff line number Diff line
@@ -151,6 +151,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);



	tmp = mmGCVM_L2_CNTL3_DEFAULT;

	if (adev->gmc.translate_further) {

		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);

	} else {

		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	}

	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);



	tmp = mmGCVM_L2_CNTL4_DEFAULT;

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+1 −0
Original line number Diff line number Diff line
@@ -309,6 +309,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 


	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);

	job->vm_needs_flush = true;

	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;

	amdgpu_ring_pad_ib(ring, &job->ibs[0]);

	r = amdgpu_job_submit(job, &adev->mman.entity,

			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+9 −0
Original line number Diff line number Diff line
@@ -137,6 +137,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);



	tmp = mmMMVM_L2_CNTL3_DEFAULT;

	if (adev->gmc.translate_further) {

		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);

	} else {

		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	}

	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);



	tmp = mmMMVM_L2_CNTL4_DEFAULT;