Commit 2cac8c44 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2019-10-31' of... 

Merge tag 'drm-intel-fixes-2019-10-31' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Fix PCH reference clock for FDI on HSW/BDW which was causing users blank screen
- Small documentation fix for TGL display PLLs

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191031171209.GA6586@intel.com
parents ec26530c 59cd826f

drivers/gpu/drm/i915/display/intel_display.c

+6 −5
Original line number Diff line number Diff line
@@ -9315,7 +9315,6 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, 
static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)

{

	struct intel_encoder *encoder;

	bool pch_ssc_in_use = false;

	bool has_fdi = false;



	for_each_intel_encoder(&dev_priv->drm, encoder) {
@@ -9343,22 +9342,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) 
	 * clock hierarchy. That would also allow us to do

	 * clock bending finally.

	 */

	dev_priv->pch_ssc_use = 0;



	if (spll_uses_pch_ssc(dev_priv)) {

		DRM_DEBUG_KMS("SPLL using PCH SSC\n");

		pch_ssc_in_use = true;

		dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);

	}



	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {

		DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");

		pch_ssc_in_use = true;

		dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);

	}



	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {

		DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");

		pch_ssc_in_use = true;

		dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);

	}



	if (pch_ssc_in_use)

	if (dev_priv->pch_ssc_use)

		return;



	if (has_fdi) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+15 −0
Original line number Diff line number Diff line
@@ -525,16 +525,31 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 
	val = I915_READ(WRPLL_CTL(id));

	I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);

	POSTING_READ(WRPLL_CTL(id));



	/*

	 * Try to set up the PCH reference clock once all DPLLs

	 * that depend on it have been shut down.

	 */

	if (dev_priv->pch_ssc_use & BIT(id))

		intel_init_pch_refclk(dev_priv);

}



static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,

				 struct intel_shared_dpll *pll)

{

	enum intel_dpll_id id = pll->info->id;

	u32 val;



	val = I915_READ(SPLL_CTL);

	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);

	POSTING_READ(SPLL_CTL);



	/*

	 * Try to set up the PCH reference clock once all DPLLs

	 * that depend on it have been shut down.

	 */

	if (dev_priv->pch_ssc_use & BIT(id))

		intel_init_pch_refclk(dev_priv);

}



static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

+2 −2
Original line number Diff line number Diff line
@@ -147,11 +147,11 @@ enum intel_dpll_id { 
	 */

	DPLL_ID_ICL_MGPLL4 = 6,

	/**

	 * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)

	 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)

	 */

	DPLL_ID_TGL_MGPLL5 = 7,

	/**

	 * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)

	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)

	 */

	DPLL_ID_TGL_MGPLL6 = 8,

};

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1723,6 +1723,8 @@ struct drm_i915_private { 
		struct work_struct idle_work;

	} gem;



	u8 pch_ssc_use;



	/* For i945gm vblank irq vs. C3 workaround */

	struct {

		struct work_struct work;