Commit e54bbcb0 authored by Philipp Zabel's avatar Philipp Zabel
Browse files

dt-bindings: reset: socfpga: Convert to yaml



Convert the device tree bindings for the Altera SOCFPGA reset manager to
YAML schema to allow participating in DT validation.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-11-p.zabel@pengutronix.de
parent 820f722c
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera SOCFPGA Reset Manager

maintainers:
  - Dinh Nguyen <dinguyen@altera.com>

properties:
  compatible:
    oneOf:
      - description: Cyclone5/Arria5/Arria10
        const: altr,rst-mgr
      - description: Stratix10 ARM64 SoC
        items:
          - const: altr,stratix10-rst-mgr
          - const: altr,rst-mgr

  reg:
    maxItems: 1

  altr,modrst-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset of the first modrst register

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - altr,modrst-offset
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    rstmgr@ffd05000 {
        compatible = "altr,rst-mgr";
        reg = <0xffd05000 0x1000>;
        altr,modrst-offset = <0x10>;
        #reset-cells = <1>;
    };
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Altera SOCFPGA Reset Manager

Required properties:
- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
	       "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
- reg : Should contain 1 register ranges(address and length)
- altr,modrst-offset : Should contain the offset of the first modrst register.
- #reset-cells: 1

Example:
	 rstmgr@ffd05000 {
		#reset-cells = <1>;
		compatible = "altr,rst-mgr";
		reg = <0xffd05000 0x1000>;
		altr,modrst-offset = <0x10>;
	};