Commit e4e36782 authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Fix off-by-one error in DML 



[WHY]
For DCN30 and later, there is no data in DML arrays indexed by state at
index num_states.

Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3577e167

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

+7 −7
Original line number Diff line number Diff line
@@ -2053,7 +2053,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
			v->DISPCLKWithoutRamping,

			v->DISPCLKDPPCLKVCOSpeed);

	v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(

			v->soc.clock_limits[mode_lib->soc.num_states].dispclk_mhz,

			v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz,

			v->DISPCLKDPPCLKVCOSpeed);

	if (v->DISPCLKWithoutRampingRoundedToDFSGranularity

			> v->MaxDispclkRoundedToDFSGranularity) {
@@ -3958,20 +3958,20 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
			for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {

				v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)

						* (1.0 + v->DISPCLKRampingMargin / 100.0);

				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]

						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {

				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]

						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {

					v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				}

				v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)

						* (1 + v->DISPCLKRampingMargin / 100.0);

				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]

						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {

				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]

						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {

					v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				}

				v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)

						* (1 + v->DISPCLKRampingMargin / 100.0);

				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]

						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {

				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]

						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {

					v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				}