Commit 3577e167 authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7 



[WHY]
DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when
changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back.

Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 39a1355f

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws) 
	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);



	/* This value is dependent on the hardware pipeline delay so set once per SOC */

	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);

	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);

}



void dcn20_disable_vga(