Commit 39a1355f authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Add interface for ADD & DROP PIXEL Registers 



[WHY]
HW has handed down a new sequence that requires access to these
registers.

v2: squash in DCN3.1 fixes (Alex)

Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b4d56e0c

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c

+26 −0
Original line number Diff line number Diff line
@@ -105,6 +105,30 @@ void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, 
			DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);

}



void dccg2_otg_add_pixel(struct dccg *dccg,

		uint32_t otg_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],

			OTG_ADD_PIXEL[otg_inst], 0,

			OTG_DROP_PIXEL[otg_inst], 0);

	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

			OTG_ADD_PIXEL[otg_inst], 1);

}



void dccg2_otg_drop_pixel(struct dccg *dccg,

		uint32_t otg_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],

			OTG_ADD_PIXEL[otg_inst], 0,

			OTG_DROP_PIXEL[otg_inst], 0);

	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

			OTG_DROP_PIXEL[otg_inst], 1);

}



void dccg2_init(struct dccg *dccg)

{

}
@@ -113,6 +137,8 @@ static const struct dccg_funcs dccg2_funcs = { 
	.update_dpp_dto = dccg2_update_dpp_dto,

	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,

	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

	.otg_add_pixel = dccg2_otg_add_pixel,

	.otg_drop_pixel = dccg2_otg_drop_pixel,

	.dccg_init = dccg2_init

};

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+47 −5
Original line number Diff line number Diff line
@@ -35,12 +35,18 @@ 
	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\

	SR(REFCLK_CNTL),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\

	SR(DISPCLK_FREQ_CHANGE_CNTL)



#define DCCG_REG_LIST_DCN2() \

	DCCG_COMMON_REG_LIST_DCN_BASE(),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 4),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 5)

	DCCG_SRII(DTO_PARAM, DPPCLK, 5),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)



#define DCCG_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -48,6 +54,9 @@ 
#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\

	.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix



#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix



#define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
@@ -68,7 +77,13 @@ 
	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\

	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\

	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\

	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh)

	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)









#define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
@@ -76,7 +91,27 @@ 
	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh)

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)



#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \

	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)





#define DCCG_REG_FIELD_LIST(type) \

	type DPPCLK0_DTO_PHASE;\
@@ -93,7 +128,9 @@ 
	type DCCG_FIFO_ERRDET_STATE;\

	type DCCG_FIFO_ERRDET_OVR_EN;\

	type DISPCLK_CHG_FWD_CORR_DISABLE;\

	type DISPCLK_FREQ_CHANGE_CNTL;

	type DISPCLK_FREQ_CHANGE_CNTL;\

	type OTG_ADD_PIXEL[MAX_PIPES];\

	type OTG_DROP_PIXEL[MAX_PIPES];



#define DCCG3_REG_FIELD_LIST(type) \

	type PHYASYMCLK_FORCE_EN;\
@@ -157,6 +194,7 @@ struct dccg_registers { 
	uint32_t DPPCLK_DTO_PARAM[6];

	uint32_t REFCLK_CNTL;

	uint32_t DISPCLK_FREQ_CHANGE_CNTL;

	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];

	uint32_t HDMICHARCLK_CLOCK_CNTL[6];

	uint32_t PHYASYMCLK_CLOCK_CNTL;

	uint32_t PHYBSYMCLK_CLOCK_CNTL;
@@ -164,7 +202,6 @@ struct dccg_registers { 
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	uint32_t PHYDSYMCLK_CLOCK_CNTL;

	uint32_t PHYESYMCLK_CLOCK_CNTL;

	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];

	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];

	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];

	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
@@ -193,6 +230,11 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, 


void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

		bool en);

void dccg2_otg_add_pixel(struct dccg *dccg,

		uint32_t otg_inst);

void dccg2_otg_drop_pixel(struct dccg *dccg,

		uint32_t otg_inst);





void dccg2_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c

+2 −0
Original line number Diff line number Diff line
@@ -101,6 +101,8 @@ static const struct dccg_funcs dccg21_funcs = { 
	.update_dpp_dto = dccg21_update_dpp_dto,

	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,

	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

	.otg_add_pixel = dccg2_otg_add_pixel,

	.otg_drop_pixel = dccg2_otg_drop_pixel,

	.dccg_init = dccg2_init

};

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+2 −2
Original line number Diff line number Diff line
@@ -448,11 +448,11 @@ static const struct dccg_registers dccg_regs = { 
};



static const struct dccg_shift dccg_shift = {

		DCCG_MASK_SH_LIST_DCN2(__SHIFT)

		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)

};



static const struct dccg_mask dccg_mask = {

		DCCG_MASK_SH_LIST_DCN2(_MASK)

		DCCG_MASK_SH_LIST_DCN2_1(_MASK)

};



#define opp_regs(id)\

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c

+2 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ static const struct dccg_funcs dccg3_funcs = { 
	.update_dpp_dto = dccg2_update_dpp_dto,

	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,

	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

	.otg_add_pixel = dccg2_otg_add_pixel,

	.otg_drop_pixel = dccg2_otg_drop_pixel,

	.dccg_init = dccg2_init

};