Commit e42faad1 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodes 



Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1de1b448

arch/arm64/boot/dts/renesas/r9a07g043.dtsi

+21 −3
Original line number Diff line number Diff line
@@ -704,18 +704,36 @@ 
		};



		ostm0: timer@12801000 {

			compatible = "renesas,r9a07g043-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801000 0x0 0x400>;

			/* place holder */

			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;

			resets = <&cpg R9A07G043_OSTM0_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm1: timer@12801400 {

			compatible = "renesas,r9a07g043-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801400 0x0 0x400>;

			/* place holder */

			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;

			resets = <&cpg R9A07G043_OSTM1_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm2: timer@12801800 {

			compatible = "renesas,r9a07g043-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801800 0x0 0x400>;

			/* place holder */

			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;

			resets = <&cpg R9A07G043_OSTM2_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};

	};