Commit 1de1b448 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node 



Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f52e1409

arch/arm64/boot/dts/renesas/r9a07g043.dtsi

+30 −1
Original line number Diff line number Diff line
@@ -291,8 +291,37 @@ 
		};



		canfd: can@10050000 {

			compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";

			reg = <0 0x10050000 0 0x8000>;

			/* place holder */

			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "g_err", "g_recc",

					  "ch0_err", "ch0_rec", "ch0_trx",

					  "ch1_err", "ch1_rec", "ch1_trx";

			clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,

				 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,

				 <&can_clk>;

			clock-names = "fck", "canfd", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;

			assigned-clock-rates = <50000000>;

			resets = <&cpg R9A07G043_CANFD_RSTP_N>,

				 <&cpg R9A07G043_CANFD_RSTC_N>;

			reset-names = "rstp_n", "rstc_n";

			power-domains = <&cpg>;

			status = "disabled";



			channel0 {

				status = "disabled";

			};

			channel1 {

				status = "disabled";

			};

		};



		i2c0: i2c@10058000 {