Commit e3272b0b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - pll driver fixup
 - meson8b clock controller dt support clean up
 - remove mipi clk from the axg clock controller

* tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson:
  clk: meson: axg: Remove MIPI enable clock gate
  clk: meson-axg: remove CLKID_MIPI_ENABLE
  dt-bindings: clock: meson8b: remove non-existing clock macros
  clk: meson: meson8b: remove compatibility code for old .dtbs
  clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
  clk: meson: clk-pll: make "ret" a signed integer
  clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
parents 5c8fe583 31035839

drivers/clk/meson/axg.c

+0 −3
Original line number Diff line number Diff line
@@ -1879,7 +1879,6 @@ static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);

static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);

static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);

static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);



/* Always On (AO) domain gates */
@@ -1974,7 +1973,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { 
		[CLKID_PCIE_REF]		= &axg_pcie_ref.hw,

		[CLKID_PCIE_CML_EN0]		= &axg_pcie_cml_en0.hw,

		[CLKID_PCIE_CML_EN1]		= &axg_pcie_cml_en1.hw,

		[CLKID_MIPI_ENABLE]		= &axg_mipi_enable.hw,

		[CLKID_GEN_CLK_SEL]		= &axg_gen_clk_sel.hw,

		[CLKID_GEN_CLK_DIV]		= &axg_gen_clk_div.hw,

		[CLKID_GEN_CLK]			= &axg_gen_clk.hw,
@@ -2115,7 +2113,6 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
	&axg_pcie_ref,

	&axg_pcie_cml_en0,

	&axg_pcie_cml_en1,

	&axg_mipi_enable,

	&axg_gen_clk_sel,

	&axg_gen_clk_div,

	&axg_gen_clk,

drivers/clk/meson/axg.h

+0 −1
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@ 
 * Register offsets from the data sheet must be multiplied by 4 before

 * adding them to the base address to get the right value.

 */

#define HHI_MIPI_CNTL0			0x00

#define HHI_GP0_PLL_CNTL		0x40

#define HHI_GP0_PLL_CNTL2		0x44

#define HHI_GP0_PLL_CNTL3		0x48

drivers/clk/meson/clk-pll.c

+6 −4
Original line number Diff line number Diff line
@@ -365,13 +365,14 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);

	unsigned int enabled, m, n, frac = 0, ret;

	unsigned int enabled, m, n, frac = 0;

	unsigned long old_rate;

	int ret;



	if (parent_rate == 0 || rate == 0)

		return -EINVAL;



	old_rate = rate;

	old_rate = clk_hw_get_rate(hw);



	ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);

	if (ret)
@@ -393,7 +394,8 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (!enabled)

		return 0;



	if (meson_clk_pll_enable(hw)) {

	ret = meson_clk_pll_enable(hw);

	if (ret) {

		pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",

			__func__, old_rate);

		/*
@@ -405,7 +407,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
		meson_clk_pll_set_rate(hw, old_rate, parent_rate);

	}



	return 0;

	return ret;

}



/*

drivers/clk/meson/meson8b.c

+5 −40
Original line number Diff line number Diff line
@@ -52,15 +52,6 @@ static const struct pll_params_table sys_pll_params_table[] = { 
	{ /* sentinel */ },

};



static struct clk_fixed_rate meson8b_xtal = {

	.fixed_rate = 24000000,

	.hw.init = &(struct clk_init_data){

		.name = "xtal",

		.num_parents = 0,

		.ops = &clk_fixed_rate_ops,

	},

};



static struct clk_regmap meson8b_fixed_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {
@@ -2715,7 +2706,6 @@ static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); 


static struct clk_hw_onecell_data meson8_hw_onecell_data = {

	.hws = {

		[CLKID_XTAL] = &meson8b_xtal.hw,

		[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,

		[CLKID_PLL_VID] = &meson8b_vid_pll.hw,

		[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
@@ -2922,7 +2912,6 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { 


static struct clk_hw_onecell_data meson8b_hw_onecell_data = {

	.hws = {

		[CLKID_XTAL] = &meson8b_xtal.hw,

		[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,

		[CLKID_PLL_VID] = &meson8b_vid_pll.hw,

		[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
@@ -3140,7 +3129,6 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 


static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {

	.hws = {

		[CLKID_XTAL] = &meson8b_xtal.hw,

		[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,

		[CLKID_PLL_VID] = &meson8b_vid_pll.hw,

		[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
@@ -3725,35 +3713,18 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = { 
	.nb.notifier_call = meson8b_cpu_clk_notifier_cb,

};



static const struct regmap_config clkc_regmap_config = {

	.reg_bits       = 32,

	.val_bits       = 32,

	.reg_stride     = 4,

};



static void __init meson8b_clkc_init_common(struct device_node *np,

			struct clk_hw_onecell_data *clk_hw_onecell_data)

{

	struct meson8b_clk_reset *rstc;

	const char *notifier_clk_name;

	struct clk *notifier_clk;

	void __iomem *clk_base;

	struct regmap *map;

	int i, ret;



	map = syscon_node_to_regmap(of_get_parent(np));

	if (IS_ERR(map)) {

		pr_info("failed to get HHI regmap - Trying obsolete regs\n");



		/* Generic clocks, PLLs and some of the reset-bits */

		clk_base = of_iomap(np, 1);

		if (!clk_base) {

			pr_err("%s: Unable to map clk base\n", __func__);

			return;

		}



		map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);

		if (IS_ERR(map))

		pr_err("failed to get HHI regmap - Trying obsolete regs\n");

		return;

	}
@@ -3778,16 +3749,10 @@ static void __init meson8b_clkc_init_common(struct device_node *np, 
		meson8b_clk_regmaps[i]->map = map;



	/*

	 * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the

	 * XTAL clock as input.

	 * register all clks and start with the first used ID (which is

	 * CLKID_PLL_FIXED)

	 */

	if (!IS_ERR(of_clk_get_by_name(np, "xtal")))

		i = CLKID_PLL_FIXED;

	else

		i = CLKID_XTAL;



	/* register all clks */

	for (; i < CLK_NR_CLKS; i++) {

	for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {

		/* array might be sparse */

		if (!clk_hw_onecell_data->hws[i])

			continue;

include/dt-bindings/clock/axg-clkc.h

+0 −1
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ 
#define CLKID_HIFI_PLL				69

#define CLKID_PCIE_CML_EN0			79

#define CLKID_PCIE_CML_EN1			80

#define CLKID_MIPI_ENABLE			81

#define CLKID_GEN_CLK				84

#define CLKID_VPU_0_SEL				92

#define CLKID_VPU_0				93