Commit 31035839 authored by Remi Pommarel's avatar Remi Pommarel Committed by Jerome Brunet
Browse files

clk: meson: axg: Remove MIPI enable clock gate 



On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.

Signed-off-by: default avatarRemi Pommarel <repk@triplefau.lt>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent dcd48b25

drivers/clk/meson/axg.c

+0 −3
Original line number Diff line number Diff line
@@ -1879,7 +1879,6 @@ static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);

static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);

static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);

static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);



/* Always On (AO) domain gates */
@@ -1974,7 +1973,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { 
		[CLKID_PCIE_REF]		= &axg_pcie_ref.hw,

		[CLKID_PCIE_CML_EN0]		= &axg_pcie_cml_en0.hw,

		[CLKID_PCIE_CML_EN1]		= &axg_pcie_cml_en1.hw,

		[CLKID_MIPI_ENABLE]		= &axg_mipi_enable.hw,

		[CLKID_GEN_CLK_SEL]		= &axg_gen_clk_sel.hw,

		[CLKID_GEN_CLK_DIV]		= &axg_gen_clk_div.hw,

		[CLKID_GEN_CLK]			= &axg_gen_clk.hw,
@@ -2115,7 +2113,6 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
	&axg_pcie_ref,

	&axg_pcie_cml_en0,

	&axg_pcie_cml_en1,

	&axg_mipi_enable,

	&axg_gen_clk_sel,

	&axg_gen_clk_div,

	&axg_gen_clk,

drivers/clk/meson/axg.h

+0 −1
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@ 
 * Register offsets from the data sheet must be multiplied by 4 before

 * adding them to the base address to get the right value.

 */

#define HHI_MIPI_CNTL0			0x00

#define HHI_GP0_PLL_CNTL		0x40

#define HHI_GP0_PLL_CNTL2		0x44

#define HHI_GP0_PLL_CNTL3		0x48