Commit e1edaeaf authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: support ASPM for some specific ASIC 



Support to program ASPM and LTR for Sienna Cichlid and forward ASIC.
Disable ASPM for Sienna Cichlid and forward ASIC by default.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 680602d6

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h

+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ struct amdgpu_nbio_funcs { 
	int (*ras_late_init)(struct amdgpu_device *adev);

	void (*enable_aspm)(struct amdgpu_device *adev,

			    bool enable);

	void (*program_aspm)(struct amdgpu_device *adev);

};



struct amdgpu_nbio {

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

+114 −0
Original line number Diff line number Diff line
@@ -34,6 +34,14 @@ 
#define smnCPM_CONTROL		0x11180460

#define smnPCIE_CNTL2		0x11180070

#define smnPCIE_LC_CNTL		0x11140280

#define smnPCIE_LC_CNTL3	0x111402d4

#define smnPCIE_LC_CNTL6	0x111402ec

#define smnPCIE_LC_CNTL7	0x111402f0

#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2	0x1014008c

#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL	0x10123538

#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP	0x10140324

#define smnPSWUSP0_PCIE_LC_CNTL2		0x111402c4

#define smnNBIF_MGCG_CTRL_LCLK			0x1013a21c



#define mmBIF_SDMA2_DOORBELL_RANGE		0x01d6

#define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX	2
@@ -350,6 +358,111 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, 
		WREG32_PCIE(smnPCIE_LC_CNTL, data);

}



static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)

{

	uint32_t def, data;



	WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);



	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);

	data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;

	if (def != data)

		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data);



	def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);

	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;

	if (def != data)

		WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);



	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);

	data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;

	if (def != data)

		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);

}



static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)

{

	uint32_t def, data;



	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);

	data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;

	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;

	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;

	if (def != data)

		WREG32_PCIE(smnPCIE_LC_CNTL, data);



	def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);

	data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;

	if (def != data)

		WREG32_PCIE(smnPCIE_LC_CNTL7, data);



	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);

	data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;

	if (def != data)

		WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);



	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);

	data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;

	if (def != data)

		WREG32_PCIE(smnPCIE_LC_CNTL3, data);



	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);

	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;

	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;

	if (def != data)

		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);



	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);

	data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;

	if (def != data)

		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);



	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);

	data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;

	if (def != data)

		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);



	WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);



	def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);

	data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |

		PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;

	data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;

	if (def != data)

		WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);



	def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);

	data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |

		PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;

	if (def != data)

		WREG32_PCIE(smnPCIE_LC_CNTL6, data);



	nbio_v2_3_program_ltr(adev);



	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);

	data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;

	data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;

	if (def != data)

		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);



	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);

	data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;

	if (def != data)

		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);



	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);

	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;

	data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;

	data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;

	if (def != data)

		WREG32_PCIE(smnPCIE_LC_CNTL, data);



	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);

	data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;

	if (def != data)

		WREG32_PCIE(smnPCIE_LC_CNTL3, data);

}



const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {

	.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,

	.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -370,4 +483,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 
	.init_registers = nbio_v2_3_init_registers,

	.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,

	.enable_aspm = nbio_v2_3_enable_aspm,

	.program_aspm =  nbio_v2_3_program_aspm,

};

drivers/gpu/drm/amd/amdgpu/nv.c

+9 −6
Original line number Diff line number Diff line
@@ -468,11 +468,14 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 


static void nv_program_aspm(struct amdgpu_device *adev)

{



	if (amdgpu_aspm == 0)

	if (amdgpu_aspm != 1)

		return;



	/* todo */

	if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&

	    !(adev->flags & AMD_IS_APU) &&

	    (adev->nbio.funcs->program_aspm))

		adev->nbio.funcs->program_aspm(adev);



}



static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -798,10 +801,10 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 
	 * The ASPM function is not fully enabled and verified on

	 * Navi yet. Temporarily skip this until ASPM enabled.

	 */

#if 0

	if (adev->nbio.funcs->enable_aspm)

	if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&

	    !(adev->flags & AMD_IS_APU) &&

	    (adev->nbio.funcs->enable_aspm))

		adev->nbio.funcs->enable_aspm(adev, !enter);

#endif



	return 0;

}