Commit e06c5f59 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Implement WM table transfer for DCN32/DCN321 



Add support for watermark table transfers.

Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 97618432

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+7 −0
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) 
}

static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

{

	unsigned int i;

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
@@ -455,6 +456,12 @@ static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 


	memset(table, 0, sizeof(*table));



	/* collect valid ranges, place in pmfw table */

	for (i = 0; i < WM_SET_COUNT; i++)

		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

			table->Watermarks.WatermarkRow[i].WmSetting = i;

			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

		}

	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);

	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);

	dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);