Commit 97618432 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Various DML fixes to enable higher timings 



Fixes to enable higher rate timings for DCN3.2.x.

Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarChaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a839a73b

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c

+2 −2
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static void dcn32_init_crb(struct hubbub *hubbub) 
	REG_SET_2(COMPBUF_RESERVED_SPACE, 0,

			COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,

			COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);

	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F);

	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);

}



static void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)
@@ -119,8 +119,8 @@ static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compb 
		ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size

				+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);

		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);

		REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100);

		hubbub2->compbuf_size_segments = compbuf_size_segments;

		ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);

	}

}

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+22 −11
Original line number Diff line number Diff line
@@ -3015,14 +3015,31 @@ int dcn32_populate_dml_pipes_from_context( 
		}

		pipe_cnt++;

	}

	context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;



	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

	switch (pipe_cnt) {

	case 1:

		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE;

		if (pipe->plane_state && !dc->debug.disable_z9_mpc) {

			if (!is_dual_plane(pipe->plane_state->format)) {

			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

				context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;

				pipes[0].pipe.src.unbounded_req_mode = true;

				if (pipe->plane_state->src_rect.width >= 5120 &&

					pipe->plane_state->src_rect.height >= 2880)

					context->bw_ctx.dml.ip.det_buffer_size_kbytes = 320; // 5K or higher

			}

		}

		break;

	case 2:

		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 2; // 576 KB (9 segments)

		break;

	case 3:

		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 3; // 384 KB (6 segments)

		break;

	case 4:

	default:

		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; // 256 KB (4 segments)

		break;

	}



	return pipe_cnt;

}
@@ -3283,7 +3300,6 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display 
	 * possible with firmware driven vertical blank stretching.

	 */

	// context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;



	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
@@ -3339,11 +3355,6 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display 
		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;



		/* cstate disabled on 201 */

//		if (dc->ctx->dce_version == DCN_VERSION_2_01)

//			cstate_en = false;





		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,

				&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,

				pipe_cnt, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+2 −25
Original line number Diff line number Diff line
@@ -1018,31 +1018,8 @@ int dcn20_populate_dml_pipes_from_context( 
			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;

		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;

		pipes[pipe_cnt].dout.dp_lanes = 4;

		if (res_ctx->pipe_ctx[i].stream->link) {

			switch (res_ctx->pipe_ctx[i].stream->link->cur_link_settings.link_rate) {

			case LINK_RATE_HIGH:

				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr;

				break;

			case LINK_RATE_HIGH2:

				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;

				break;

			case LINK_RATE_HIGH3:

				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr3;

				break;

			case LINK_RATE_UHBR10:

				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr10;

				break;

			case LINK_RATE_UHBR13_5:

				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr13p5;

				break;

			case LINK_RATE_UHBR20:

				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr20;

				break;

			default:

		if (res_ctx->pipe_ctx[i].stream->link)

			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;

				break;

			}

		}

		pipes[pipe_cnt].dout.is_virtual = 0;

		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;

		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;