Commit e0396943 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Yunying Sun
Browse files

x86/cpu: Fix Gracemont uarch 

mainline inclusion
from mainline-v6.6-rc1
commit 882cdb06
category: feature
feature: SRF core PMU support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RWG5
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=882cdb06b668488a42ef717a260c05ba7dc43a49



Intel-SIG: commit 882cdb06 x86/cpu: Fix Gracemont uarch
Backport as a dependency for Sierra Forrest core PMU support.

-------------------------------------

Alderlake N is an E-core only product using Gracemont
micro-architecture. It fits the pre-existing naming scheme perfectly
fine, adhere to it.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent 1e394dcb

arch/x86/events/intel/core.c

+1 −1
Original line number Diff line number Diff line
@@ -6122,7 +6122,7 @@ __init int intel_pmu_init(void) 
		name = "Tremont";

		break;



	case INTEL_FAM6_ALDERLAKE_N:

	case INTEL_FAM6_ATOM_GRACEMONT:

		x86_pmu.mid_ack = true;

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

arch/x86/events/intel/cstate.c

+1 −1
Original line number Diff line number Diff line
@@ -671,6 +671,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&glm_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	&glm_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&glm_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&adl_cstates),



	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,		&icl_cstates),
@@ -683,7 +684,6 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,	&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE,		&adl_cstates),

arch/x86/events/intel/uncore.c

+1 −1
Original line number Diff line number Diff line
@@ -1839,12 +1839,12 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&tgl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,	&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&snr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&adl_uncore_init),

	{},

};

MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);

arch/x86/events/msr.c

+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static bool test_intel(int idx, void *data) 
	case INTEL_FAM6_TIGERLAKE:

	case INTEL_FAM6_ALDERLAKE:

	case INTEL_FAM6_ALDERLAKE_L:

	case INTEL_FAM6_ALDERLAKE_N:

	case INTEL_FAM6_ATOM_GRACEMONT:

	case INTEL_FAM6_RAPTORLAKE:

	case INTEL_FAM6_RAPTORLAKE_P:

	case INTEL_FAM6_METEORLAKE:

arch/x86/include/asm/intel-family.h

+2 −1
Original line number Diff line number Diff line
@@ -111,7 +111,6 @@ 


#define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */

#define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */

#define INTEL_FAM6_ALDERLAKE_N		0xBE



#define INTEL_FAM6_RAPTORLAKE		0xB7

#define INTEL_FAM6_RAPTORLAKE_P		0xBA
@@ -146,6 +145,8 @@ 
#define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */

#define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */



#define INTEL_FAM6_ATOM_GRACEMONT	0xBE /* Alderlake N */



#define INTEL_FAM6_SIERRAFOREST_X	0xAF



#define INTEL_FAM6_GRANDRIDGE		0xB6