Commit dfa7c521 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-01-12' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- PSR fixes and improvements for selective fetch (Jose)
- GVT build fixed and cleanup (Jani)
- RKL display fixes (Lee, Matt)
- DSI fix (Hans)
- Panel Power and Backlight fixes (Anshuman, Jani)
- RPM fix (Chris)
- Fix HTI port checking (Jose)
- Clean-up in cursor code (Ville)
- Once again, trying to use fast+narrow link on eDP (Ville)
- DG1 display fix (Matt)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210112175151.GA90999@intel.com
parents 2ce542e5 cce73665

drivers/gpu/drm/i915/Makefile

+1 −9
Original line number Diff line number Diff line
@@ -285,15 +285,7 @@ obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o 


# exclude some broken headers from the test coverage

no-header-test := \

	display/intel_vbt_defs.h \

	gvt/execlist.h \

	gvt/fb_decoder.h \

	gvt/gtt.h \

	gvt/gvt.h \

	gvt/interrupt.h \

	gvt/mmio_context.h \

	gvt/mpt.h \

	gvt/scheduler.h

	display/intel_vbt_defs.h



extra-$(CONFIG_DRM_I915_WERROR) += \

	$(patsubst %.h,%.hdrtest, $(filter-out $(no-header-test), \

drivers/gpu/drm/i915/display/intel_bios.c

+10 −0
Original line number Diff line number Diff line
@@ -1623,6 +1623,13 @@ static const u8 icp_ddc_pin_map[] = { 
	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,

};



static const u8 rkl_pch_tgp_ddc_pin_map[] = {

	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,

	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,

	[RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,

	[RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,

};



static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)

{

	const u8 *ddc_pin_map;
@@ -1630,6 +1637,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) 


	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {

		return vbt_pin;

	} else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {

		ddc_pin_map = rkl_pch_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);

	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {

		ddc_pin_map = icp_ddc_pin_map;

		n_entries = ARRAY_SIZE(icp_ddc_pin_map);

drivers/gpu/drm/i915/display/intel_cursor.c

+3 −3
Original line number Diff line number Diff line
@@ -492,8 +492,8 @@ static void i9xx_update_cursor(struct intel_plane *plane, 
	unsigned long irqflags;



	if (plane_state && plane_state->uapi.visible) {

		unsigned width = drm_rect_width(&plane_state->uapi.dst);

		unsigned height = drm_rect_height(&plane_state->uapi.dst);

		int width = drm_rect_width(&plane_state->uapi.dst);

		int height = drm_rect_height(&plane_state->uapi.dst);



		cntl = plane_state->ctl |

			i9xx_cursor_ctl_crtc(crtc_state);
@@ -522,7 +522,7 @@ static void i9xx_update_cursor(struct intel_plane *plane, 
	 * cursor that doesn't appear to move, or even change

	 * shape. Thus we always write CURBASE.

	 *

	 * The other registers are armed by by the CURBASE write

	 * The other registers are armed by the CURBASE write

	 * except when the plane is getting enabled at which time

	 * the CURCNTR write arms the update.

	 */

drivers/gpu/drm/i915/display/intel_ddi.c

+74 −5
Original line number Diff line number Diff line
@@ -611,6 +611,34 @@ static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] 
	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */

};



static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */

	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */

	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */

	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */

	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */

	{ 0xC, 0x60, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */

	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */

	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */

	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */

	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */

	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */

	{ 0xC, 0x58, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */

	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



struct icl_mg_phy_ddi_buf_trans {

	u32 cri_txdeemph_override_11_6;

	u32 cri_txdeemph_override_5_0;
@@ -766,6 +794,34 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_ho 
	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 2	1	*/

};



static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x2F, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */

	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */

	{ 0x6, 0x7D, 0x2A, 0x00, 0x15 },	/* 350   900      8.2   */

	{ 0xA, 0x4C, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x73, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */

	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */

	{ 0xC, 0x6E, 0x3E, 0x00, 0x01 },	/* 650   700      0.6   */

	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x50, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */

	{ 0xC, 0x61, 0x33, 0x00, 0x0C },	/* 350   700      6.0   */

	{ 0x6, 0x7F, 0x2E, 0x00, 0x11 },	/* 350   900      8.2   */

	{ 0xA, 0x47, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x5F, 0x38, 0x00, 0x07 },	/* 500   700      2.9   */

	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */

	{ 0xC, 0x5F, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */

	{ 0x6, 0x7E, 0x36, 0x00, 0x09 },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)

{

	return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1093,6 +1149,12 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 
	} else if (dev_priv->vbt.edp.low_vswing) {

		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);

		return icl_combo_phy_ddi_translations_edp_hbr2;

	} else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) {

		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3);

		return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3;

	} else if (IS_DG1(dev_priv)) {

		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_rbr_hbr);

		return dg1_combo_phy_ddi_translations_dp_rbr_hbr;

	}



	return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
@@ -1259,18 +1321,26 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (crtc_state->port_clock > 270000) {

		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {

		if (IS_ROCKETLAKE(dev_priv)) {

			*n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3);

			return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3;

		} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {

			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);

			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;

		} else {

			*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);

			return tgl_combo_phy_ddi_translations_dp_hbr2;

		}

	} else {

		if (IS_ROCKETLAKE(dev_priv)) {

			*n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr);

			return rkl_combo_phy_ddi_translations_dp_hbr;

		} else {

			*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);

			return tgl_combo_phy_ddi_translations_dp_hbr;

		}

	}

}



static const struct cnl_ddi_buf_trans *

tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
@@ -5285,8 +5355,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) 
static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)

{

	return i915->hti_state & HDPORT_ENABLED &&

		(i915->hti_state & HDPORT_PHY_USED_DP(phy) ||

		 i915->hti_state & HDPORT_PHY_USED_HDMI(phy));

	       i915->hti_state & HDPORT_DDI_USED(phy);

}



static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_display.c

+49 −29
Original line number Diff line number Diff line
@@ -3752,33 +3752,19 @@ static int intel_plane_max_height(struct intel_plane *plane, 
		return INT_MAX;

}









static int skl_check_main_surface(struct intel_plane_state *plane_state)









int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,









				 int *x, int *y, u32 *offset)









{









	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);









	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);









	const struct drm_framebuffer *fb = plane_state->hw.fb;









	unsigned int rotation = plane_state->hw.rotation;









	int x = plane_state->uapi.src.x1 >> 16;









	int y = plane_state->uapi.src.y1 >> 16;









	int w = drm_rect_width(&plane_state->uapi.src) >> 16;









	int h = drm_rect_height(&plane_state->uapi.src) >> 16;









	int min_width = intel_plane_min_width(plane, fb, 0, rotation);









	int max_width = intel_plane_max_width(plane, fb, 0, rotation);









	int max_height = intel_plane_max_height(plane, fb, 0, rotation);









	int aux_plane = intel_main_to_aux_plane(fb, 0);









	u32 aux_offset = plane_state->color_plane[aux_plane].offset;









	u32 alignment, offset;

















	if (w > max_width || w < min_width || h > max_height) {









		drm_dbg_kms(&dev_priv->drm,









			    "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",









			    w, h, min_width, max_width, max_height);









		return -EINVAL;









	}









	const int aux_plane = intel_main_to_aux_plane(fb, 0);









	const u32 aux_offset = plane_state->color_plane[aux_plane].offset;









	const u32 alignment = intel_surf_alignment(fb, 0);









	const int w = drm_rect_width(&plane_state->uapi.src) >> 16;

















	intel_add_fb_offsets(&x, &y, plane_state, 0);









	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);









	alignment = intel_surf_alignment(fb, 0);









	intel_add_fb_offsets(x, y, plane_state, 0);









	*offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);









	if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))









		return -EINVAL;
















@@ -3787,9 +3773,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)







	 * main surface offset, and it must be non-negative. Make









	 * sure that is what we will get.









	 */









	if (aux_plane && offset > aux_offset)









		offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,









							   offset, aux_offset & ~(alignment - 1));









	if (aux_plane && *offset > aux_offset)









		*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,









							    *offset,









							    aux_offset & ~(alignment - 1));

















	/*









	 * When using an X-tiled surface, the plane blows up








@@ -3800,18 +3787,51 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)







	if (fb->modifier == I915_FORMAT_MOD_X_TILED) {









		int cpp = fb->format->cpp[0];

















		while ((x + w) * cpp > plane_state->color_plane[0].stride) {









			if (offset == 0) {









		while ((*x + w) * cpp > plane_state->color_plane[0].stride) {









			if (*offset == 0) {









				drm_dbg_kms(&dev_priv->drm,









					    "Unable to find suitable display surface offset due to X-tiling\n");









				return -EINVAL;









			}

















			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,









								   offset, offset - alignment);









			*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,









								    *offset,









								    *offset - alignment);









		}









	}

















	return 0;









}

















static int skl_check_main_surface(struct intel_plane_state *plane_state)









{









	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);









	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);









	const struct drm_framebuffer *fb = plane_state->hw.fb;









	const unsigned int rotation = plane_state->hw.rotation;









	int x = plane_state->uapi.src.x1 >> 16;









	int y = plane_state->uapi.src.y1 >> 16;









	const int w = drm_rect_width(&plane_state->uapi.src) >> 16;









	const int h = drm_rect_height(&plane_state->uapi.src) >> 16;









	const int min_width = intel_plane_min_width(plane, fb, 0, rotation);









	const int max_width = intel_plane_max_width(plane, fb, 0, rotation);









	const int max_height = intel_plane_max_height(plane, fb, 0, rotation);









	const int aux_plane = intel_main_to_aux_plane(fb, 0);









	const u32 alignment = intel_surf_alignment(fb, 0);









	u32 offset;









	int ret;

















	if (w > max_width || w < min_width || h > max_height) {









		drm_dbg_kms(&dev_priv->drm,









			    "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",









			    w, h, min_width, max_width, max_height);









		return -EINVAL;









	}

















	ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);









	if (ret)









		return ret;

















	/*









	 * CCS AUX surface doesn't have its own x/y offsets, we must make sure









	 * they match with the main surface x/y offsets.