Commit 2ce542e5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.12-2021-01-08' of... 

Merge tag 'amd-drm-next-5.12-2021-01-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.12-2021-01-08:

amdgpu:
- Rework IH ring handling on vega and navi
- Rework HDP handling for vega and navi
- swSMU documenation updates
- Overdrive support for Sienna Cichlid and newer asics
- swSMU updates for vangogh
- swSMU updates for renoir
- Enable FP16 on DCE8-11
- Misc code cleanups and bug fixes

radeon:
- Fixes for platforms that can't access PCI resources correctly
- Misc code cleanups

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210108221811.3868-1-alexander.deucher@amd.com


Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parents cb3cfbf7 044a48f4

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ amdgpu-y += \ 
	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \

	nbio_v7_2.o dimgrey_cavefish_reg_init.o

	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o



# add DF block

amdgpu-y += \
@@ -97,6 +97,7 @@ amdgpu-y += \ 
	tonga_ih.o \

	cz_ih.o \

	vega10_ih.o \

	vega20_ih.o \

	navi10_ih.o



# add PSP block

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+9 −3
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
#include "amdgpu_gfx.h"

#include "amdgpu_sdma.h"

#include "amdgpu_nbio.h"

#include "amdgpu_hdp.h"

#include "amdgpu_dm.h"

#include "amdgpu_virt.h"

#include "amdgpu_csa.h"
@@ -106,6 +107,7 @@ 
#include "amdgpu_gfxhub.h"

#include "amdgpu_df.h"

#include "amdgpu_smuio.h"

#include "amdgpu_hdp.h"



#define MAX_GPU_INSTANCE		16
@@ -607,7 +609,6 @@ struct amdgpu_asic_funcs { 
	/* invalidate hdp read cache */

	void (*invalidate_hdp)(struct amdgpu_device *adev,

			       struct amdgpu_ring *ring);

	void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);

	/* check if the asic needs a full reset of if soft reset will work */

	bool (*need_full_reset)(struct amdgpu_device *adev);

	/* initialize doorbell layout for specific asic*/
@@ -920,6 +921,9 @@ struct amdgpu_device { 
	/* nbio */

	struct amdgpu_nbio		nbio;



	/* hdp */

	struct amdgpu_hdp		hdp;



	/* smuio */

	struct amdgpu_smuio		smuio;
@@ -1201,8 +1205,10 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))

#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))

#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))

#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))

#define amdgpu_asic_flush_hdp(adev, r) \

	((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))

#define amdgpu_asic_invalidate_hdp(adev, r) \

	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))

#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))

#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))

#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ 
#include "amdgpu_amdkfd.h"

#include "gc/gc_10_1_0_offset.h"

#include "gc/gc_10_1_0_sh_mask.h"

#include "navi10_enum.h"

#include "athub/athub_2_0_0_offset.h"

#include "athub/athub_2_0_0_sh_mask.h"

#include "oss/osssys_5_0_0_offset.h"

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+0 −1
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ 
#include "amdgpu_amdkfd.h"

#include "gc/gc_10_3_0_offset.h"

#include "gc/gc_10_3_0_sh_mask.h"

#include "navi10_enum.h"

#include "oss/osssys_5_0_0_offset.h"

#include "oss/osssys_5_0_0_sh_mask.h"

#include "soc15_common.h"

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

+3 −2
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev) 
	u8 header[AMD_VBIOS_SIGNATURE_END+1] = {0};

	int len;



	if (!adev->asic_funcs->read_bios_from_rom)

	if (!adev->asic_funcs || !adev->asic_funcs->read_bios_from_rom)

		return false;



	/* validate VBIOS signature */
@@ -348,7 +348,8 @@ static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev) 
	if (adev->flags & AMD_IS_APU)

		return igp_read_bios_from_vram(adev);

	else

		return amdgpu_asic_read_disabled_bios(adev);

		return (!adev->asic_funcs || !adev->asic_funcs->read_disabled_bios) ?

			false : amdgpu_asic_read_disabled_bios(adev);

}



#ifdef CONFIG_ACPI