Commit df45da57 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "ACPI:

   - Improve error reporting when failing to manage SDEI on AGDI device
     removal

  Assembly routines:

   - Improve register constraints so that the compiler can make use of
     the zero register instead of moving an immediate #0 into a GPR

   - Allow the compiler to allocate the registers used for CAS
     instructions

  CPU features and system registers:

   - Cleanups to the way in which CPU features are identified from the
     ID register fields

   - Extend system register definition generation to handle Enum types
     when defining shared register fields

   - Generate definitions for new _EL2 registers and add new fields for
     ID_AA64PFR1_EL1

   - Allow SVE to be disabled separately from SME on the kernel
     command-line

  Tracing:

   - Support for "direct calls" in ftrace, which enables BPF tracing for
     arm64

  Kdump:

   - Don't bother unmapping the crashkernel from the linear mapping,
     which then allows us to use huge (block) mappings and reduce TLB
     pressure when a crashkernel is loaded.

  Memory management:

   - Try again to remove data cache invalidation from the coherent DMA
     allocation path

   - Simplify the fixmap code by mapping at page granularity

   - Allow the kfence pool to be allocated early, preventing the rest of
     the linear mapping from being forced to page granularity

  Perf and PMU:

   - Move CPU PMU code out to drivers/perf/ where it can be reused by
     the 32-bit ARM architecture when running on ARMv8 CPUs

   - Fix race between CPU PMU probing and pKVM host de-privilege

   - Add support for Apple M2 CPU PMU

   - Adjust the generic PERF_COUNT_HW_BRANCH_INSTRUCTIONS event
     dynamically, depending on what the CPU actually supports

   - Minor fixes and cleanups to system PMU drivers

  Stack tracing:

   - Use the XPACLRI instruction to strip PAC from pointers, rather than
     rolling our own function in C

   - Remove redundant PAC removal for toolchains that handle this in
     their builtins

   - Make backtracing more resilient in the face of instrumentation

  Miscellaneous:

   - Fix single-step with KGDB

   - Remove harmless warning when 'nokaslr' is passed on the kernel
     command-line

   - Minor fixes and cleanups across the board"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (72 commits)
  KVM: arm64: Ensure CPU PMU probes before pKVM host de-privilege
  arm64: kexec: include reboot.h
  arm64: delete dead code in this_cpu_set_vectors()
  arm64/cpufeature: Use helper macro to specify ID register for capabilites
  drivers/perf: hisi: add NULL check for name
  drivers/perf: hisi: Remove redundant initialized of pmu->name
  arm64/cpufeature: Consistently use symbolic constants for min_field_value
  arm64/cpufeature: Pull out helper for CPUID register definitions
  arm64/sysreg: Convert HFGITR_EL2 to automatic generation
  ACPI: AGDI: Improve error reporting for problems during .remove()
  arm64: kernel: Fix kernel warning when nokaslr is passed to commandline
  perf/arm-cmn: Fix port detection for CMN-700
  arm64: kgdb: Set PSTATE.SS to 1 to re-enable single-step
  arm64: move PAC masks to <asm/pointer_auth.h>
  arm64: use XPACLRI to strip PAC
  arm64: avoid redundant PAC stripping in __builtin_return_address()
  arm64/sme: Fix some comments of ARM SME
  arm64/signal: Alloc tpidr2 sigframe after checking system_supports_tpidr2()
  arm64/signal: Use system_supports_tpidr2() to check TPIDR2
  arm64/idreg: Don't disable SME when disabling SVE
  ...
parents 53b5e72b eeb3557c

Documentation/devicetree/bindings/arm/pmu.yaml

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ properties: 
    items:

      - enum:

          - apm,potenza-pmu

          - apple,avalanche-pmu

          - apple,blizzard-pmu

          - apple,firestorm-pmu

          - apple,icestorm-pmu

          - arm,armv8-pmuv3 # Only for s/w models

arch/arm/include/asm/arm_pmuv3.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2012 ARM Ltd.

 */



#ifndef __ASM_PMUV3_H

#define __ASM_PMUV3_H



#include <asm/cp15.h>

#include <asm/cputype.h>



#define PMCCNTR			__ACCESS_CP15_64(0, c9)



#define PMCR			__ACCESS_CP15(c9,  0, c12, 0)

#define PMCNTENSET		__ACCESS_CP15(c9,  0, c12, 1)

#define PMCNTENCLR		__ACCESS_CP15(c9,  0, c12, 2)

#define PMOVSR			__ACCESS_CP15(c9,  0, c12, 3)

#define PMSELR			__ACCESS_CP15(c9,  0, c12, 5)

#define PMCEID0			__ACCESS_CP15(c9,  0, c12, 6)

#define PMCEID1			__ACCESS_CP15(c9,  0, c12, 7)

#define PMXEVTYPER		__ACCESS_CP15(c9,  0, c13, 1)

#define PMXEVCNTR		__ACCESS_CP15(c9,  0, c13, 2)

#define PMUSERENR		__ACCESS_CP15(c9,  0, c14, 0)

#define PMINTENSET		__ACCESS_CP15(c9,  0, c14, 1)

#define PMINTENCLR		__ACCESS_CP15(c9,  0, c14, 2)

#define PMMIR			__ACCESS_CP15(c9,  0, c14, 6)

#define PMCCFILTR		__ACCESS_CP15(c14, 0, c15, 7)



#define PMEVCNTR0		__ACCESS_CP15(c14, 0, c8, 0)

#define PMEVCNTR1		__ACCESS_CP15(c14, 0, c8, 1)

#define PMEVCNTR2		__ACCESS_CP15(c14, 0, c8, 2)

#define PMEVCNTR3		__ACCESS_CP15(c14, 0, c8, 3)

#define PMEVCNTR4		__ACCESS_CP15(c14, 0, c8, 4)

#define PMEVCNTR5		__ACCESS_CP15(c14, 0, c8, 5)

#define PMEVCNTR6		__ACCESS_CP15(c14, 0, c8, 6)

#define PMEVCNTR7		__ACCESS_CP15(c14, 0, c8, 7)

#define PMEVCNTR8		__ACCESS_CP15(c14, 0, c9, 0)

#define PMEVCNTR9		__ACCESS_CP15(c14, 0, c9, 1)

#define PMEVCNTR10		__ACCESS_CP15(c14, 0, c9, 2)

#define PMEVCNTR11		__ACCESS_CP15(c14, 0, c9, 3)

#define PMEVCNTR12		__ACCESS_CP15(c14, 0, c9, 4)

#define PMEVCNTR13		__ACCESS_CP15(c14, 0, c9, 5)

#define PMEVCNTR14		__ACCESS_CP15(c14, 0, c9, 6)

#define PMEVCNTR15		__ACCESS_CP15(c14, 0, c9, 7)

#define PMEVCNTR16		__ACCESS_CP15(c14, 0, c10, 0)

#define PMEVCNTR17		__ACCESS_CP15(c14, 0, c10, 1)

#define PMEVCNTR18		__ACCESS_CP15(c14, 0, c10, 2)

#define PMEVCNTR19		__ACCESS_CP15(c14, 0, c10, 3)

#define PMEVCNTR20		__ACCESS_CP15(c14, 0, c10, 4)

#define PMEVCNTR21		__ACCESS_CP15(c14, 0, c10, 5)

#define PMEVCNTR22		__ACCESS_CP15(c14, 0, c10, 6)

#define PMEVCNTR23		__ACCESS_CP15(c14, 0, c10, 7)

#define PMEVCNTR24		__ACCESS_CP15(c14, 0, c11, 0)

#define PMEVCNTR25		__ACCESS_CP15(c14, 0, c11, 1)

#define PMEVCNTR26		__ACCESS_CP15(c14, 0, c11, 2)

#define PMEVCNTR27		__ACCESS_CP15(c14, 0, c11, 3)

#define PMEVCNTR28		__ACCESS_CP15(c14, 0, c11, 4)

#define PMEVCNTR29		__ACCESS_CP15(c14, 0, c11, 5)

#define PMEVCNTR30		__ACCESS_CP15(c14, 0, c11, 6)



#define PMEVTYPER0		__ACCESS_CP15(c14, 0, c12, 0)

#define PMEVTYPER1		__ACCESS_CP15(c14, 0, c12, 1)

#define PMEVTYPER2		__ACCESS_CP15(c14, 0, c12, 2)

#define PMEVTYPER3		__ACCESS_CP15(c14, 0, c12, 3)

#define PMEVTYPER4		__ACCESS_CP15(c14, 0, c12, 4)

#define PMEVTYPER5		__ACCESS_CP15(c14, 0, c12, 5)

#define PMEVTYPER6		__ACCESS_CP15(c14, 0, c12, 6)

#define PMEVTYPER7		__ACCESS_CP15(c14, 0, c12, 7)

#define PMEVTYPER8		__ACCESS_CP15(c14, 0, c13, 0)

#define PMEVTYPER9		__ACCESS_CP15(c14, 0, c13, 1)

#define PMEVTYPER10		__ACCESS_CP15(c14, 0, c13, 2)

#define PMEVTYPER11		__ACCESS_CP15(c14, 0, c13, 3)

#define PMEVTYPER12		__ACCESS_CP15(c14, 0, c13, 4)

#define PMEVTYPER13		__ACCESS_CP15(c14, 0, c13, 5)

#define PMEVTYPER14		__ACCESS_CP15(c14, 0, c13, 6)

#define PMEVTYPER15		__ACCESS_CP15(c14, 0, c13, 7)

#define PMEVTYPER16		__ACCESS_CP15(c14, 0, c14, 0)

#define PMEVTYPER17		__ACCESS_CP15(c14, 0, c14, 1)

#define PMEVTYPER18		__ACCESS_CP15(c14, 0, c14, 2)

#define PMEVTYPER19		__ACCESS_CP15(c14, 0, c14, 3)

#define PMEVTYPER20		__ACCESS_CP15(c14, 0, c14, 4)

#define PMEVTYPER21		__ACCESS_CP15(c14, 0, c14, 5)

#define PMEVTYPER22		__ACCESS_CP15(c14, 0, c14, 6)

#define PMEVTYPER23		__ACCESS_CP15(c14, 0, c14, 7)

#define PMEVTYPER24		__ACCESS_CP15(c14, 0, c15, 0)

#define PMEVTYPER25		__ACCESS_CP15(c14, 0, c15, 1)

#define PMEVTYPER26		__ACCESS_CP15(c14, 0, c15, 2)

#define PMEVTYPER27		__ACCESS_CP15(c14, 0, c15, 3)

#define PMEVTYPER28		__ACCESS_CP15(c14, 0, c15, 4)

#define PMEVTYPER29		__ACCESS_CP15(c14, 0, c15, 5)

#define PMEVTYPER30		__ACCESS_CP15(c14, 0, c15, 6)



#define RETURN_READ_PMEVCNTRN(n) \

	return read_sysreg(PMEVCNTR##n)

static unsigned long read_pmevcntrn(int n)

{

	PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);

	return 0;

}



#define WRITE_PMEVCNTRN(n) \

	write_sysreg(val, PMEVCNTR##n)

static void write_pmevcntrn(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVCNTRN);

}



#define WRITE_PMEVTYPERN(n) \

	write_sysreg(val, PMEVTYPER##n)

static void write_pmevtypern(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVTYPERN);

}



static inline unsigned long read_pmmir(void)

{

	return read_sysreg(PMMIR);

}



static inline u32 read_pmuver(void)

{

	/* PMUVers is not a signed field */

	u32 dfr0 = read_cpuid_ext(CPUID_EXT_DFR0);



	return (dfr0 >> 24) & 0xf;

}



static inline void write_pmcr(u32 val)

{

	write_sysreg(val, PMCR);

}



static inline u32 read_pmcr(void)

{

	return read_sysreg(PMCR);

}



static inline void write_pmselr(u32 val)

{

	write_sysreg(val, PMSELR);

}



static inline void write_pmccntr(u64 val)

{

	write_sysreg(val, PMCCNTR);

}



static inline u64 read_pmccntr(void)

{

	return read_sysreg(PMCCNTR);

}



static inline void write_pmxevcntr(u32 val)

{

	write_sysreg(val, PMXEVCNTR);

}



static inline u32 read_pmxevcntr(void)

{

	return read_sysreg(PMXEVCNTR);

}



static inline void write_pmxevtyper(u32 val)

{

	write_sysreg(val, PMXEVTYPER);

}



static inline void write_pmcntenset(u32 val)

{

	write_sysreg(val, PMCNTENSET);

}



static inline void write_pmcntenclr(u32 val)

{

	write_sysreg(val, PMCNTENCLR);

}



static inline void write_pmintenset(u32 val)

{

	write_sysreg(val, PMINTENSET);

}



static inline void write_pmintenclr(u32 val)

{

	write_sysreg(val, PMINTENCLR);

}



static inline void write_pmccfiltr(u32 val)

{

	write_sysreg(val, PMCCFILTR);

}



static inline void write_pmovsclr(u32 val)

{

	write_sysreg(val, PMOVSR);

}



static inline u32 read_pmovsclr(void)

{

	return read_sysreg(PMOVSR);

}



static inline void write_pmuserenr(u32 val)

{

	write_sysreg(val, PMUSERENR);

}



static inline u32 read_pmceid0(void)

{

	return read_sysreg(PMCEID0);

}



static inline u32 read_pmceid1(void)

{

	return read_sysreg(PMCEID1);

}



static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}

static inline void kvm_clr_pmu_events(u32 clr) {}

static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)

{

	return false;

}



/* PMU Version in DFR Register */

#define ARMV8_PMU_DFR_VER_NI        0

#define ARMV8_PMU_DFR_VER_V3P4      0x5

#define ARMV8_PMU_DFR_VER_V3P5      0x6

#define ARMV8_PMU_DFR_VER_IMP_DEF   0xF



static inline bool pmuv3_implemented(int pmuver)

{

	return !(pmuver == ARMV8_PMU_DFR_VER_IMP_DEF ||

		 pmuver == ARMV8_PMU_DFR_VER_NI);

}



static inline bool is_pmuv3p4(int pmuver)

{

	return pmuver >= ARMV8_PMU_DFR_VER_V3P4;

}



static inline bool is_pmuv3p5(int pmuver)

{

	return pmuver >= ARMV8_PMU_DFR_VER_V3P5;

}



#endif

arch/arm/mm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -403,7 +403,7 @@ config CPU_V6K 
	select CPU_THUMB_CAPABLE

	select CPU_TLB_V6 if MMU



# ARMv7

# ARMv7 and ARMv8 architectures

config CPU_V7

	bool

	select CPU_32v6K

arch/arm64/Kconfig

+18 −0
Original line number Diff line number Diff line
@@ -186,6 +186,10 @@ config ARM64 
	select HAVE_DEBUG_KMEMLEAK

	select HAVE_DMA_CONTIGUOUS

	select HAVE_DYNAMIC_FTRACE

	select HAVE_DYNAMIC_FTRACE_WITH_ARGS \

		if $(cc-option,-fpatchable-function-entry=2)

	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \

		if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS

	select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \

		if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \

		    !CC_OPTIMIZE_FOR_SIZE)
@@ -363,6 +367,20 @@ config ARCH_PROC_KCORE_TEXT 
config BROKEN_GAS_INST

	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)



config BUILTIN_RETURN_ADDRESS_STRIPS_PAC

	bool

	# Clang's __builtin_return_adddress() strips the PAC since 12.0.0

	# https://reviews.llvm.org/D75044

	default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)

	# GCC's __builtin_return_address() strips the PAC since 11.1.0,

	# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier

	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891

	default y if CC_IS_GCC && (GCC_VERSION >= 110100)

	default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)

	default y if CC_IS_GCC && (GCC_VERSION >=  90400) && (GCC_VERSION < 100000)

	default y if CC_IS_GCC && (GCC_VERSION >=  80500) && (GCC_VERSION <  90000)

	default n



config KASAN_SHADOW_OFFSET

	hex

	depends on KASAN_GENERIC || KASAN_SW_TAGS

arch/arm64/include/asm/arm_pmuv3.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2012 ARM Ltd.

 */



#ifndef __ASM_PMUV3_H

#define __ASM_PMUV3_H



#include <linux/kvm_host.h>



#include <asm/cpufeature.h>

#include <asm/sysreg.h>



#define RETURN_READ_PMEVCNTRN(n) \

	return read_sysreg(pmevcntr##n##_el0)

static unsigned long read_pmevcntrn(int n)

{

	PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);

	return 0;

}



#define WRITE_PMEVCNTRN(n) \

	write_sysreg(val, pmevcntr##n##_el0)

static void write_pmevcntrn(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVCNTRN);

}



#define WRITE_PMEVTYPERN(n) \

	write_sysreg(val, pmevtyper##n##_el0)

static void write_pmevtypern(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVTYPERN);

}



static inline unsigned long read_pmmir(void)

{

	return read_cpuid(PMMIR_EL1);

}



static inline u32 read_pmuver(void)

{

	u64 dfr0 = read_sysreg(id_aa64dfr0_el1);



	return cpuid_feature_extract_unsigned_field(dfr0,

			ID_AA64DFR0_EL1_PMUVer_SHIFT);

}



static inline void write_pmcr(u32 val)

{

	write_sysreg(val, pmcr_el0);

}



static inline u32 read_pmcr(void)

{

	return read_sysreg(pmcr_el0);

}



static inline void write_pmselr(u32 val)

{

	write_sysreg(val, pmselr_el0);

}



static inline void write_pmccntr(u64 val)

{

	write_sysreg(val, pmccntr_el0);

}



static inline u64 read_pmccntr(void)

{

	return read_sysreg(pmccntr_el0);

}



static inline void write_pmxevcntr(u32 val)

{

	write_sysreg(val, pmxevcntr_el0);

}



static inline u32 read_pmxevcntr(void)

{

	return read_sysreg(pmxevcntr_el0);

}



static inline void write_pmxevtyper(u32 val)

{

	write_sysreg(val, pmxevtyper_el0);

}



static inline void write_pmcntenset(u32 val)

{

	write_sysreg(val, pmcntenset_el0);

}



static inline void write_pmcntenclr(u32 val)

{

	write_sysreg(val, pmcntenclr_el0);

}



static inline void write_pmintenset(u32 val)

{

	write_sysreg(val, pmintenset_el1);

}



static inline void write_pmintenclr(u32 val)

{

	write_sysreg(val, pmintenclr_el1);

}



static inline void write_pmccfiltr(u32 val)

{

	write_sysreg(val, pmccfiltr_el0);

}



static inline void write_pmovsclr(u32 val)

{

	write_sysreg(val, pmovsclr_el0);

}



static inline u32 read_pmovsclr(void)

{

	return read_sysreg(pmovsclr_el0);

}



static inline void write_pmuserenr(u32 val)

{

	write_sysreg(val, pmuserenr_el0);

}



static inline u32 read_pmceid0(void)

{

	return read_sysreg(pmceid0_el0);

}



static inline u32 read_pmceid1(void)

{

	return read_sysreg(pmceid1_el0);

}



static inline bool pmuv3_implemented(int pmuver)

{

	return !(pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||

		 pmuver == ID_AA64DFR0_EL1_PMUVer_NI);

}



static inline bool is_pmuv3p4(int pmuver)

{

	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4;

}



static inline bool is_pmuv3p5(int pmuver)

{

	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5;

}



#endif