Commit dec15c99 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra: cclk: Add helpers for handling PLLX rate changes 



CCLK should be re-parented away from PLLX if PLLX's rate is changing.
The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus
CCLK will be re-parented to PLLP before PLLX rate-change begins and then
switched back to PLLX after the rate-change completion. This patch adds
helper functions which perform CCLK re-parenting, these helpers will be
utilized by further patches.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarNicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 9157abe7

drivers/clk/tegra/clk-tegra-super-cclk.c

+34 −0
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ 


#define SUPER_CDIV_ENB		BIT(31)



static struct tegra_clk_super_mux *cclk_super;

static bool cclk_on_pllx;



static u8 cclk_super_get_parent(struct clk_hw *hw)

{

	return tegra_clk_super_ops.get_parent(hw);
@@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, 
	struct clk_init_data init;

	u32 val;



	if (WARN_ON(cclk_super))

		return ERR_PTR(-EBUSY);



	super = kzalloc(sizeof(*super), GFP_KERNEL);

	if (!super)

		return ERR_PTR(-ENOMEM);
@@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, 
	clk = clk_register(NULL, &super->hw);

	if (IS_ERR(clk))

		kfree(super);

	else

		cclk_super = super;



	return clk;

}



int tegra_cclk_pre_pllx_rate_change(void)

{

	if (IS_ERR_OR_NULL(cclk_super))

		return -EINVAL;



	if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX)

		cclk_on_pllx = true;

	else

		cclk_on_pllx = false;



	/*

	 * CPU needs to be temporarily re-parented away from PLLX if PLLX

	 * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs.

	 */

	if (cclk_on_pllx)

		cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX);



	return 0;

}



void tegra_cclk_post_pllx_rate_change(void)

{

	if (cclk_on_pllx)

		cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX);

}

drivers/clk/tegra/clk.h

+2 −0
Original line number Diff line number Diff line
@@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, 
		const char * const *parent_names, u8 num_parents,

		unsigned long flags, void __iomem *reg, u8 clk_super_flags,

		spinlock_t *lock);

int tegra_cclk_pre_pllx_rate_change(void);

void tegra_cclk_post_pllx_rate_change(void);



/**

 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC