Commit 9157abe7 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
Browse files

clk: tegra: pll: Add pre/post rate-change hooks 



There is a need to temporarily re-parent CCLK away from PLLX if PLLX's
rate is about to change. The newly introduced PLL pre/post rate-change
hooks allow to handle such case.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarNicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 16415679

drivers/clk/tegra/clk-pll.c

+11 −1
Original line number Diff line number Diff line
@@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 


	state = clk_pll_is_enabled(hw);



	if (state && pll->params->pre_rate_change) {

		ret = pll->params->pre_rate_change();

		if (WARN_ON(ret))

			return ret;

	}



	_get_pll_mnp(pll, &old_cfg);



	if (state && pll->params->defaults_set && pll->params->dyn_ramp &&

			(cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {

		ret = pll->params->dyn_ramp(pll, cfg);

		if (!ret)

			return 0;

			goto done;

	}



	if (state) {
@@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 
		pll_clk_start_ss(pll);

	}



done:

	if (state && pll->params->post_rate_change)

		pll->params->post_rate_change();



	return ret;

}

drivers/clk/tegra/clk.h

+6 −0
Original line number Diff line number Diff line
@@ -266,6 +266,10 @@ struct tegra_clk_pll; 
 *				disabled.

 * @dyn_ramp:			Callback which can be used to define a custom

 *				dynamic ramp function for a given PLL.

 * @pre_rate_change:		Callback which is invoked just before changing

 *				PLL's rate.

 * @post_rate_change:		Callback which is invoked right after changing

 *				PLL's rate.

 *

 * Flags:

 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -342,6 +346,8 @@ struct tegra_clk_pll_params { 
	void	(*set_defaults)(struct tegra_clk_pll *pll);

	int	(*dyn_ramp)(struct tegra_clk_pll *pll,

			struct tegra_clk_pll_freq_table *cfg);

	int	(*pre_rate_change)(void);

	void	(*post_rate_change)(void);

};



#define TEGRA_PLL_USE_LOCK BIT(0)