Commit dd6ad051 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.13-2021-05-19' of... 

Merge tag 'amd-drm-fixes-5.13-2021-05-19' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.13-2021-05-19:

amdgpu:
- Fix downscaling ratio on DCN3.x
- Fix for non-4K pages
- PCO/RV compute hang fix
- Dongle fix
- Aldebaran codec query support
- Refcount leak fix
- Use after free fix
- Navi12 golden settings updates
- GPU reset fixes

radeon:
- Fix for imported BO handling

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210520022500.4023-1-alexander.deucher@amd.com
parents 4996c342 a2b4785f

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −1
Original line number Diff line number Diff line
@@ -4479,7 +4479,6 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, 
			r = amdgpu_ib_ring_tests(tmp_adev);

			if (r) {

				dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);

				r = amdgpu_device_ip_suspend(tmp_adev);

				need_full_reset = true;

				r = -EAGAIN;

				goto end;

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

+3 −0
Original line number Diff line number Diff line
@@ -288,10 +288,13 @@ static int amdgpufb_create(struct drm_fb_helper *helper, 
static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)

{

	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;

	int i;



	drm_fb_helper_unregister_fbi(&rfbdev->helper);



	if (rfb->base.obj[0]) {

		for (i = 0; i < rfb->base.format->num_planes; i++)

			drm_gem_object_put(rfb->base.obj[0]);

		amdgpufb_destroy_pinned_object(rfb->base.obj[0]);

		rfb->base.obj[0] = NULL;

		drm_framebuffer_unregister_private(&rfb->base);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+2 −1
Original line number Diff line number Diff line
@@ -225,7 +225,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 
	*addr += mm_cur->start & ~PAGE_MASK;



	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);

	num_bytes = num_pages * 8;

	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;



	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,

				     AMDGPU_IB_POOL_DELAYED, &job);
@@ -1210,6 +1210,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 
	if (gtt && gtt->userptr) {

		amdgpu_ttm_tt_set_user_pages(ttm, NULL);

		kfree(ttm->sg);

		ttm->sg = NULL;

		ttm->page_flags &= ~TTM_PAGE_FLAG_SG;

		return;

	}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −2
Original line number Diff line number Diff line
@@ -1395,9 +1395,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
@@ -1415,12 +1416,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)

};



static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+7 −3
Original line number Diff line number Diff line
@@ -4943,7 +4943,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 
	amdgpu_gfx_rlc_enter_safe_mode(adev);



	/* Enable 3D CGCG/CGLS */

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {

	if (enable) {

		/* write cmd to clear cgcg/cgls ov */

		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

		/* unset CGCG override */
@@ -4955,8 +4955,12 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 
		/* enable 3Dcgcg FSM(0x0000363f) */

		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);



		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)

			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |

				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;

		else

			data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;



		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)

			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |

				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;