Commit dcfde8f6 authored by Marijn Suijten's avatar Marijn Suijten Committed by Rob Clark
Browse files

drm/msm/dsi/phy: Reindent and reflow multiline function calls 



The commit 613cbd1d ("drm/msm/dsi: use devm_clk_*register to registe
DSI PHY clocks") introduced the devm_ prefix to clk_hw registration
calls, without updating the indentation of the arguments on the
following lines.

Similarly commit e55b3fbb ("drm/msm/dsi: drop PLL accessor
functions") moved from pll_write to dsi_phy_write without updating the
indentation of followup arguments either.

Preparing for a series that heavily touches the clk calls, reflow and
reindent function calls that are adhering to an 80-char column limit by
spanning multiple lines.  Where function names are very long the
arguments are indented with a fixed number of two tab characters instead
of aligning with the opening parenthesis of the function call.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/491931/
Link: https://lore.kernel.org/r/20220629225331.357308-5-marijn.suijten@somainline.org


[DB: adjusted commit message to make checkpatch happy]
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent aa0bff10

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+47 −49
Original line number Diff line number Diff line
@@ -216,13 +216,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) 
	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,

		      0xba);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,

		      0x0c);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,

		      0x08);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,

		      0xfa);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,

		      0x4c);

	dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
@@ -598,9 +601,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);

	snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);



	hw = devm_clk_hw_register_divider(dev, clk_name,

				     parent, CLK_SET_RATE_PARENT,

				     pll_10nm->phy->pll_base +

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

			CLK_SET_RATE_PARENT, pll_10nm->phy->pll_base +

				REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,

			0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	if (IS_ERR(hw)) {
@@ -614,10 +616,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	/* BIT CLK: DIV_CTRL_3_0 */

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

			CLK_SET_RATE_PARENT,

				     pll_10nm->phy->base +

				     REG_DSI_10nm_PHY_CMN_CLK_CFG0,

				     0, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_10nm->postdiv_lock);

			pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,

			0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;
@@ -664,7 +664,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 


	hw = devm_clk_hw_register_mux(dev, clk_name,

			((const char *[]){

				 parent, parent2, parent3, parent4

				parent, parent2, parent3, parent4,

			}), 4, 0, pll_10nm->phy->base +

				REG_DSI_10nm_PHY_CMN_CLK_CFG1,

			0, 2, 0, NULL);
@@ -677,11 +677,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);



	/* PIX CLK DIV : DIV_CTRL_7_4*/

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

				     0, pll_10nm->phy->base +

					REG_DSI_10nm_PHY_CMN_CLK_CFG0,

				     4, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_10nm->postdiv_lock);

	hw = devm_clk_hw_register_divider(dev, clk_name, parent, 0,

			pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,

			4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+5 −4
Original line number Diff line number Diff line
@@ -952,7 +952,8 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, 


	if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {

		DRM_DEV_ERROR(&phy->pdev->dev,

			"%s: D-PHY timing calculation failed\n", __func__);

			      "%s: D-PHY timing calculation failed\n",

			      __func__);

		return -EINVAL;

	}

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

+36 −37
Original line number Diff line number Diff line
@@ -320,8 +320,8 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) 
		dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);



		/* poll for PLL ready status */

		locked = pll_28nm_poll_for_ready(pll_28nm,

						max_reads, timeout_us);

		locked = pll_28nm_poll_for_ready(pll_28nm, max_reads,

						 timeout_us);

		if (locked)

			break;
@@ -547,9 +547,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 


	snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);

	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);

	hw = devm_clk_hw_register_divider(dev, clk_name,

			parent1, CLK_SET_RATE_PARENT,

			pll_28nm->phy->pll_base +

	hw = devm_clk_hw_register_divider(dev, clk_name, parent1,

			CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +

				REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,

			0, 4, 0, NULL);

	if (IS_ERR(hw))
@@ -557,16 +556,15 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 


	snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);

	snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name,

			parent1, CLK_SET_RATE_PARENT,

			1, 2);

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1,

			CLK_SET_RATE_PARENT, 1, 2);

	if (IS_ERR(hw))

		return PTR_ERR(hw);



	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);

	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);

	hw = devm_clk_hw_register_divider(dev, clk_name,

				parent1, 0, pll_28nm->phy->pll_base +

	hw = devm_clk_hw_register_divider(dev, clk_name, parent1, 0,

			pll_28nm->phy->pll_base +

				REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,

			0, 8, 0, NULL);

	if (IS_ERR(hw))
@@ -578,7 +576,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 
	snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);

	hw = devm_clk_hw_register_mux(dev, clk_name,

			((const char *[]){

				parent1, parent2

				parent1, parent2,

			}), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +

				REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);

	if (IS_ERR(hw))
@@ -586,8 +584,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 


	snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);

	snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id);

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name,

				parent1, CLK_SET_RATE_PARENT, 1, 4);

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1,

			CLK_SET_RATE_PARENT, 1, 4);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	provided_clocks[DSI_BYTE_PLL_CLK] = hw;
@@ -713,7 +711,8 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, 


	if (msm_dsi_dphy_timing_calc(timing, clk_req)) {

		DRM_DEV_ERROR(&phy->pdev->dev,

			"%s: D-PHY timing calculation failed\n", __func__);

			      "%s: D-PHY timing calculation failed\n",

			      __func__);

		return -EINVAL;

	}

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c

+32 −31
Original line number Diff line number Diff line
@@ -446,8 +446,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 


	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id + 1);

	/* DIV3 */

	hw = devm_clk_hw_register_divider(dev, clk_name,

				parent_name, 0, pll_28nm->phy->pll_base +

	hw = devm_clk_hw_register_divider(dev, clk_name, parent_name, 0,

			pll_28nm->phy->pll_base +

				REG_DSI_28nm_8960_PHY_PLL_CTRL_10,

			0, 8, 0, NULL);

	if (IS_ERR(hw))
@@ -602,7 +602,8 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, 


	if (msm_dsi_dphy_timing_calc(timing, clk_req)) {

		DRM_DEV_ERROR(&phy->pdev->dev,

			"%s: D-PHY timing calculation failed\n", __func__);

			      "%s: D-PHY timing calculation failed\n",

			      __func__);

		return -EINVAL;

	}

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+41 −43
Original line number Diff line number Diff line
@@ -245,7 +245,8 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *confi 
	void __iomem *base = pll->phy->pll_base;



	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,

		      config->decimal_div_start);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,

		      config->frac_div_start & 0xff);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
@@ -254,8 +255,10 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *confi 
		      (config->frac_div_start & 0x30000) >> 16);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, pll->phy->cphy_mode ? 0x00 : 0x10);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1,

		      pll->phy->cphy_mode ? 0x00 : 0x10);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,

		      config->pll_clock_inverters);

}



static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -612,9 +615,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 
	snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);

	snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id);



	hw = devm_clk_hw_register_divider(dev, clk_name,

				     parent, CLK_SET_RATE_PARENT,

				     pll_7nm->phy->pll_base +

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

			CLK_SET_RATE_PARENT, pll_7nm->phy->pll_base +

				REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,

			0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	if (IS_ERR(hw)) {
@@ -628,10 +630,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 
	/* BIT CLK: DIV_CTRL_3_0 */

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

			CLK_SET_RATE_PARENT,

				     pll_7nm->phy->base +

				     REG_DSI_7nm_PHY_CMN_CLK_CFG0,

				     0, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_7nm->postdiv_lock);

			pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,

			0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;
@@ -705,11 +705,9 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 
	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);



	/* PIX CLK DIV : DIV_CTRL_7_4*/

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

				     0, pll_7nm->phy->base +

					REG_DSI_7nm_PHY_CMN_CLK_CFG0,

				     4, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_7nm->postdiv_lock);

	hw = devm_clk_hw_register_divider(dev, clk_name, parent, 0,

			pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,

			4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;