Commit 613cbd1d authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks 



Use devres-enabled version of clock registration functions. This lets us
remove dsi_pll destroy callbacks completely.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-12-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 5d134596

drivers/gpu/drm/msm/dsi/dsi.h

+0 −4
Original line number Diff line number Diff line
@@ -95,13 +95,9 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); 
/* dsi pll */

struct msm_dsi_pll;

#ifdef CONFIG_DRM_MSM_DSI_PLL

void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);

void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);

int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);

#else

static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)

{

}

static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)

{

}

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+0 −2
Original line number Diff line number Diff line
@@ -744,7 +744,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 
fail:

	if (phy->pll) {

		of_clk_del_provider(dev->of_node);

		msm_dsi_pll_destroy(phy->pll);

		phy->pll = NULL;

	}
@@ -757,7 +756,6 @@ static int dsi_phy_driver_remove(struct platform_device *pdev) 


	if (phy && phy->pll) {

		of_clk_del_provider(pdev->dev.of_node);

		msm_dsi_pll_destroy(phy->pll);

		phy->pll = NULL;

	}

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ struct msm_dsi_phy_ops { 
struct msm_dsi_pll_ops {

	int (*enable_seq)(struct msm_dsi_pll *pll);

	void (*disable_seq)(struct msm_dsi_pll *pll);

	void (*destroy)(struct msm_dsi_pll *pll);

	void (*save_state)(struct msm_dsi_pll *pll);

	int (*restore_state)(struct msm_dsi_pll *pll);

};

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+16 −68
Original line number Diff line number Diff line
@@ -103,15 +103,6 @@ struct dsi_pll_10nm { 
	struct dsi_pll_config pll_configuration;

	struct dsi_pll_regs reg_setup;



	/* private clocks: */

	struct clk_hw *out_div_clk_hw;

	struct clk_hw *bit_clk_hw;

	struct clk_hw *byte_clk_hw;

	struct clk_hw *by_2_bit_clk_hw;

	struct clk_hw *post_out_div_clk_hw;

	struct clk_hw *pclk_mux_hw;

	struct clk_hw *out_dsiclk_hw;



	struct pll_10nm_cached_state cached_state;



	enum msm_dsi_phy_usecase uc;
@@ -614,22 +605,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, 
	return 0;

}



static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)

{

	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);



	DBG("DSI PLL%d", pll_10nm->id);



	clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);

	clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);

	clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);

	clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);

	clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);

	clk_hw_unregister_divider(pll_10nm->bit_clk_hw);

	clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);

	clk_hw_unregister(&pll_10nm->base.clk_hw);

}



/*

 * The post dividers and mux clocks are created using the standard divider and

 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
@@ -656,30 +631,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);

	pll_10nm->base.clk_hw.init = &vco_init;



	ret = clk_hw_register(dev, &pll_10nm->base.clk_hw);

	ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);

	if (ret)

		return ret;



	snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);

	snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);



	hw = clk_hw_register_divider(dev, clk_name,

	hw = devm_clk_hw_register_divider(dev, clk_name,

				     parent, CLK_SET_RATE_PARENT,

				     pll_10nm->mmio +

				     REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,

				     0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_base_clk_hw;

		goto fail;

	}



	pll_10nm->out_div_clk_hw = hw;



	snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);



	/* BIT CLK: DIV_CTRL_3_0 */

	hw = clk_hw_register_divider(dev, clk_name, parent,

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

				     CLK_SET_RATE_PARENT,

				     pll_10nm->phy_cmn_mmio +

				     REG_DSI_10nm_PHY_CMN_CLK_CFG0,
@@ -687,56 +660,49 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
				     &pll_10nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_out_div_clk_hw;

		goto fail;

	}



	pll_10nm->bit_clk_hw = hw;



	snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);



	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */

	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					  CLK_SET_RATE_PARENT, 1, 8);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_bit_clk_hw;

		goto fail;

	}



	pll_10nm->byte_clk_hw = hw;

	provided_clocks[DSI_BYTE_PLL_CLK] = hw;



	snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);



	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					  0, 1, 2);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_byte_clk_hw;

		goto fail;

	}



	pll_10nm->by_2_bit_clk_hw = hw;



	snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);



	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					  0, 1, 4);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_by_2_bit_clk_hw;

		goto fail;

	}



	pll_10nm->post_out_div_clk_hw = hw;



	snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);

	snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);

	snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);

	snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);



	hw = clk_hw_register_mux(dev, clk_name,

	hw = devm_clk_hw_register_mux(dev, clk_name,

				 ((const char *[]){

				 parent, parent2, parent3, parent4

				 }), 4, 0, pll_10nm->phy_cmn_mmio +
@@ -744,44 +710,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
				 0, 2, 0, NULL);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_post_out_div_clk_hw;

		goto fail;

	}



	pll_10nm->pclk_mux_hw = hw;



	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);



	/* PIX CLK DIV : DIV_CTRL_7_4*/

	hw = clk_hw_register_divider(dev, clk_name, parent,

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

				     0, pll_10nm->phy_cmn_mmio +

					REG_DSI_10nm_PHY_CMN_CLK_CFG0,

				     4, 4, CLK_DIVIDER_ONE_BASED,

				     &pll_10nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto err_pclk_mux_hw;

		goto fail;

	}



	pll_10nm->out_dsiclk_hw = hw;

	provided_clocks[DSI_PIXEL_PLL_CLK] = hw;



	return 0;



err_pclk_mux_hw:

	clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);

err_post_out_div_clk_hw:

	clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);

err_by_2_bit_clk_hw:

	clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);

err_byte_clk_hw:

	clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);

err_bit_clk_hw:

	clk_hw_unregister_divider(pll_10nm->bit_clk_hw);

err_out_div_clk_hw:

	clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);

err_base_clk_hw:

	clk_hw_unregister(&pll_10nm->base.clk_hw);

fail:



	return ret;

}
@@ -1060,7 +1010,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { 
		.pll_init = dsi_pll_10nm_init,

	},

	.pll_ops = {

		.destroy = dsi_pll_10nm_destroy,

		.save_state = dsi_pll_10nm_save_state,

		.restore_state = dsi_pll_10nm_restore_state,

	},
@@ -1085,7 +1034,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { 
		.pll_init = dsi_pll_10nm_init,

	},

	.pll_ops = {

		.destroy = dsi_pll_10nm_destroy,

		.save_state = dsi_pll_10nm_save_state,

		.restore_state = dsi_pll_10nm_restore_state,

	},

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+4 −31
Original line number Diff line number Diff line
@@ -133,10 +133,6 @@ struct dsi_pll_14nm { 
	u64 vco_current_rate;

	u64 vco_ref_clk_rate;



	/* private clocks: */

	struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];

	u32 num_hws;



	struct pll_14nm_cached_state cached_state;



	enum msm_dsi_phy_usecase uc;
@@ -872,15 +868,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, 
	return 0;

}



static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)

{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);

	int num_hws = pll_14nm->num_hws;



	while (num_hws--)

		clk_hw_unregister(pll_14nm->hws[num_hws]);

}



static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,

						const char *name,

						const char *parent_name,
@@ -910,7 +897,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, 
	pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;

	pll_postdiv->hw.init = &postdiv_init;



	ret = clk_hw_register(dev, &pll_postdiv->hw);

	ret = devm_clk_hw_register(dev, &pll_postdiv->hw);

	if (ret)

		return ERR_PTR(ret);
@@ -928,9 +915,7 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov 
		.ops = &clk_ops_dsi_pll_14nm_vco,

	};

	struct device *dev = &pll_14nm->pdev->dev;

	struct clk_hw **hws = pll_14nm->hws;

	struct clk_hw *hw;

	int num = 0;

	int ret;



	DBG("DSI%d", pll_14nm->id);
@@ -938,12 +923,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov 
	snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);

	pll_14nm->base.clk_hw.init = &vco_init;



	ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);

	ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);

	if (ret)

		return ret;



	hws[num++] = &pll_14nm->base.clk_hw;



	snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);

	snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
@@ -953,18 +936,15 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov 
	if (IS_ERR(hw))

		return PTR_ERR(hw);



	hws[num++] = hw;



	snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);

	snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);



	/* DSI Byte clock = VCO_CLK / N1 / 8 */

	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					  CLK_SET_RATE_PARENT, 1, 8);

	if (IS_ERR(hw))

		return PTR_ERR(hw);



	hws[num++] = hw;

	provided_clocks[DSI_BYTE_PLL_CLK] = hw;



	snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
@@ -974,12 +954,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov 
	 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider

	 * on the way. Don't let it set parent.

	 */

	hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);

	if (IS_ERR(hw))

		return PTR_ERR(hw);



	hws[num++] = hw;



	snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);

	snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
@@ -991,11 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov 
	if (IS_ERR(hw))

		return PTR_ERR(hw);



	hws[num++] = hw;

	provided_clocks[DSI_PIXEL_PLL_CLK]	= hw;



	pll_14nm->num_hws = num;



	return 0;

}
@@ -1184,7 +1159,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 
		.pll_init = dsi_pll_14nm_init,

	},

	.pll_ops = {

		.destroy = dsi_pll_14nm_destroy,

		.save_state = dsi_pll_14nm_save_state,

		.restore_state = dsi_pll_14nm_restore_state,

		.disable_seq = dsi_pll_14nm_disable_seq,
@@ -1211,7 +1185,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { 
		.pll_init = dsi_pll_14nm_init,

	},

	.pll_ops = {

		.destroy = dsi_pll_14nm_destroy,

		.save_state = dsi_pll_14nm_save_state,

		.restore_state = dsi_pll_14nm_restore_state,

		.disable_seq = dsi_pll_14nm_disable_seq,