Commit dc7d19d2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.18-2022-04-06' of... 

Merge tag 'amd-drm-fixes-5.18-2022-04-06' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.18-2022-04-06:

amdgpu:
- VCN 3.0 fixes
- DCN 3.1.5 fix
- Misc display fixes
- GC 10.3 golden register fix
- Suspend fix
- SMU 10 fix

amdkfd:
- Event fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220406170441.5779-1-alexander.deucher@amd.com
parents c6b035e6 2f25d8ce

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+2 −2
Original line number Diff line number Diff line
@@ -300,8 +300,8 @@ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 
void amdgpu_ring_commit(struct amdgpu_ring *ring);

void amdgpu_ring_undo(struct amdgpu_ring *ring);

int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,

		     unsigned int ring_size, struct amdgpu_irq_src *irq_src,

		     unsigned int irq_type, unsigned int prio,

		     unsigned int max_dw, struct amdgpu_irq_src *irq_src,

		     unsigned int irq_type, unsigned int hw_prio,

		     atomic_t *sched_score);

void amdgpu_ring_fini(struct amdgpu_ring *ring);

void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+7 −0
Original line number Diff line number Diff line
@@ -159,6 +159,7 @@ 
#define AMDGPU_VCN_MULTI_QUEUE_FLAG	(1 << 8)

#define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)

#define AMDGPU_VCN_FW_LOGGING_FLAG	(1 << 10)

#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)



#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001

#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
@@ -279,6 +280,11 @@ struct amdgpu_fw_shared_fw_logging { 
	uint32_t size;

};



struct amdgpu_fw_shared_smu_interface_info {

	uint8_t smu_interface_type;

	uint8_t padding[3];

};



struct amdgpu_fw_shared {

	uint32_t present_flag_0;

	uint8_t pad[44];
@@ -287,6 +293,7 @@ struct amdgpu_fw_shared { 
	struct amdgpu_fw_shared_multi_queue multi_queue;

	struct amdgpu_fw_shared_sw_ring sw_ring;

	struct amdgpu_fw_shared_fw_logging fw_log;

	struct amdgpu_fw_shared_smu_interface_info smu_interface_info;

};



struct amdgpu_vcn_fwlog {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+3 −3
Original line number Diff line number Diff line
@@ -3293,7 +3293,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
@@ -3429,7 +3429,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
@@ -3454,7 +3454,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+6 −1
Original line number Diff line number Diff line
@@ -219,6 +219,11 @@ static int vcn_v3_0_sw_init(void *handle) 
					     cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |

					     cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);

		fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);

		fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;

		if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 2))

			fw_shared->smu_interface_info.smu_interface_type = 2;

		else if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 1))

			fw_shared->smu_interface_info.smu_interface_type = 1;



		if (amdgpu_vcnfw_log)

			amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
@@ -1483,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 
	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};

	uint32_t tmp;



	vcn_v3_0_pause_dpg_mode(adev, 0, &state);

	vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);



	/* Wait for power status to be 1 */

	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c

+15 −9
Original line number Diff line number Diff line
@@ -247,15 +247,6 @@ int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) 
		return ret;

	}



	ret = anon_inode_getfd(kfd_smi_name, &kfd_smi_ev_fops, (void *)client,

			       O_RDWR);

	if (ret < 0) {

		kfifo_free(&client->fifo);

		kfree(client);

		return ret;

	}

	*fd = ret;



	init_waitqueue_head(&client->wait_queue);

	spin_lock_init(&client->lock);

	client->events = 0;
@@ -265,5 +256,20 @@ int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd) 
	list_add_rcu(&client->list, &dev->smi_clients);

	spin_unlock(&dev->smi_lock);



	ret = anon_inode_getfd(kfd_smi_name, &kfd_smi_ev_fops, (void *)client,

			       O_RDWR);

	if (ret < 0) {

		spin_lock(&dev->smi_lock);

		list_del_rcu(&client->list);

		spin_unlock(&dev->smi_lock);



		synchronize_rcu();



		kfifo_free(&client->fifo);

		kfree(client);

		return ret;

	}

	*fd = ret;



	return 0;

}