Commit dc63fbe3 authored by Xiongfeng Wang's avatar Xiongfeng Wang Committed by Xiongfeng Wang
Browse files

PCI: Fail MSI-X mapping if MSI-X Table offset is out of range of BAR space 

euler inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I8XWBL


CVE: NA

----------------------------------------

This patch add check for the offset of MSI-X Table. If it is out of range
of the BAR space BIR selects, we just fail this MSI-X mapping.

Signed-off-by: default avatarXiongfeng Wang <xiongfeng.wang@linaro.org>
Reviewed-by: default avatarHanjun Guo <guohanjun@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
 Conflicts:
	drivers/pci/msi.c
Signed-off-by: default avatarXiongfeng Wang <xiongfeng.wang@linaro.org>
parent 070dcfd3

drivers/pci/msi/msi.c

+6 −0
Original line number Diff line number Diff line
@@ -564,6 +564,12 @@ static void __iomem *msix_map_region(struct pci_dev *dev, 
		return NULL;



	table_offset &= PCI_MSIX_TABLE_OFFSET;

	if (table_offset >= pci_resource_len(dev, bir)) {

		dev_err(&dev->dev,

			"MSI-X Table offset is out of range of BAR:%d!\n",

			bir);

		return NULL;

	}

	phys_addr = pci_resource_start(dev, bir) + table_offset;



	return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);