Commit dbe2422b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: merge all MDP TOP registers to dpu_hwio.h 



There is a separate header containing some of MDP TOP register
definitions, dpu_hwio.h. Move missing register definitions from
dpu_hw_top.c to the mentioned header.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/514242/
Link: https://lore.kernel.org/r/20221207012231.112059-9-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 0eda3c6c

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

+0 −25
Original line number Diff line number Diff line
@@ -7,40 +7,17 @@ 
#include "dpu_hw_top.h"

#include "dpu_kms.h"



#define SSPP_SPARE                        0x28



#define FLD_SPLIT_DISPLAY_CMD             BIT(1)

#define FLD_SMART_PANEL_FREE_RUN          BIT(2)

#define FLD_INTF_1_SW_TRG_MUX             BIT(4)

#define FLD_INTF_2_SW_TRG_MUX             BIT(8)

#define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF



#define DANGER_STATUS                     0x360

#define SAFE_STATUS                       0x364



#define TE_LINE_INTERVAL                  0x3F4



#define TRAFFIC_SHAPER_EN                 BIT(31)

#define TRAFFIC_SHAPER_RD_CLIENT(num)     (0x030 + (num * 4))

#define TRAFFIC_SHAPER_WR_CLIENT(num)     (0x060 + (num * 4))

#define TRAFFIC_SHAPER_FIXPOINT_FACTOR    4



#define MDP_WD_TIMER_0_CTL                0x380

#define MDP_WD_TIMER_0_CTL2               0x384

#define MDP_WD_TIMER_0_LOAD_VALUE         0x388

#define MDP_WD_TIMER_1_CTL                0x390

#define MDP_WD_TIMER_1_CTL2               0x394

#define MDP_WD_TIMER_1_LOAD_VALUE         0x398

#define MDP_WD_TIMER_2_CTL                0x420

#define MDP_WD_TIMER_2_CTL2               0x424

#define MDP_WD_TIMER_2_LOAD_VALUE         0x428

#define MDP_WD_TIMER_3_CTL                0x430

#define MDP_WD_TIMER_3_CTL2               0x434

#define MDP_WD_TIMER_3_LOAD_VALUE         0x438

#define MDP_WD_TIMER_4_CTL                0x440

#define MDP_WD_TIMER_4_CTL2               0x444

#define MDP_WD_TIMER_4_LOAD_VALUE         0x448



#define MDP_TICK_COUNT                    16

#define XO_CLK_RATE                       19200

#define MS_TICKS_IN_SEC                   1000
@@ -48,8 +25,6 @@ 
#define CALCULATE_WD_LOAD_VALUE(fps) \

	((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))



#define DCE_SEL                           0x450



static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,

		struct split_pipe_cfg *cfg)

{

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

+18 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#define INTR_CLEAR                      0x018

#define INTR2_EN                        0x008

#define INTR2_STATUS                    0x00c

#define SSPP_SPARE                      0x028

#define INTR2_CLEAR                     0x02c

#define HIST_INTR_EN                    0x01c

#define HIST_INTR_STATUS                0x020
@@ -28,7 +29,15 @@ 
#define DSPP_IGC_COLOR0_RAM_LUTN        0x300

#define DSPP_IGC_COLOR1_RAM_LUTN        0x304

#define DSPP_IGC_COLOR2_RAM_LUTN        0x308

#define DANGER_STATUS                   0x360

#define SAFE_STATUS                     0x364

#define HW_EVENTS_CTL                   0x37C

#define MDP_WD_TIMER_0_CTL              0x380

#define MDP_WD_TIMER_0_CTL2             0x384

#define MDP_WD_TIMER_0_LOAD_VALUE       0x388

#define MDP_WD_TIMER_1_CTL              0x390

#define MDP_WD_TIMER_1_CTL2             0x394

#define MDP_WD_TIMER_1_LOAD_VALUE       0x398

#define CLK_CTRL3                       0x3A8

#define CLK_STATUS3                     0x3AC

#define CLK_CTRL4                       0x3B0
@@ -43,6 +52,15 @@ 
#define HDMI_DP_CORE_SELECT             0x408

#define MDP_OUT_CTL_0                   0x410

#define MDP_VSYNC_SEL                   0x414

#define MDP_WD_TIMER_2_CTL              0x420

#define MDP_WD_TIMER_2_CTL2             0x424

#define MDP_WD_TIMER_2_LOAD_VALUE       0x428

#define MDP_WD_TIMER_3_CTL              0x430

#define MDP_WD_TIMER_3_CTL2             0x434

#define MDP_WD_TIMER_3_LOAD_VALUE       0x438

#define MDP_WD_TIMER_4_CTL              0x440

#define MDP_WD_TIMER_4_CTL2             0x444

#define MDP_WD_TIMER_4_LOAD_VALUE       0x448

#define DCE_SEL                         0x450



#endif /*_DPU_HWIO_H */