Commit 0eda3c6c authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

dt-bindings: display/msm: add support for the display on SM8450 



Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8450 platform.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/514234/
Link: https://lore.kernel.org/r/20221207012231.112059-5-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 73162e5d

Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml

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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8450 Display DPU



maintainers:

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>



$ref: /schemas/display/msm/dpu-common.yaml#



properties:

  compatible:

    const: qcom,sm8450-dpu



  reg:

    items:

      - description: Address offset and size for mdp register set

      - description: Address offset and size for vbif register set



  reg-names:

    items:

      - const: mdp

      - const: vbif



  clocks:

    items:

      - description: Display hf axi

      - description: Display sf axi

      - description: Display ahb

      - description: Display lut

      - description: Display core

      - description: Display vsync



  clock-names:

    items:

      - const: bus

      - const: nrt_bus

      - const: iface

      - const: lut

      - const: core

      - const: vsync



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8450-dispcc.h>

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-controller@ae01000 {

        compatible = "qcom,sm8450-dpu";

        reg = <0x0ae01000 0x8f000>,

              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";



        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                <&gcc GCC_DISP_SF_AXI_CLK>,

                <&dispcc DISP_CC_MDSS_AHB_CLK>,

                <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                <&dispcc DISP_CC_MDSS_MDP_CLK>,

                <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

        clock-names = "bus",

                      "nrt_bus",

                      "iface",

                      "lut",

                      "core",

                      "vsync";



        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

        assigned-clock-rates = <19200000>;



        operating-points-v2 = <&mdp_opp_table>;

        power-domains = <&rpmhpd SM8450_MMCX>;



        interrupt-parent = <&mdss>;

        interrupts = <0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                dpu_intf1_out: endpoint {

                    remote-endpoint = <&dsi0_in>;

                };

            };



            port@1 {

                reg = <1>;

                dpu_intf2_out: endpoint {

                    remote-endpoint = <&dsi1_in>;

                };

            };

        };



        mdp_opp_table: opp-table {

            compatible = "operating-points-v2";



            opp-172000000{

                opp-hz = /bits/ 64 <172000000>;

                required-opps = <&rpmhpd_opp_low_svs_d1>;

            };



            opp-200000000 {

                opp-hz = /bits/ 64 <200000000>;

                required-opps = <&rpmhpd_opp_low_svs>;

            };



            opp-325000000 {

                opp-hz = /bits/ 64 <325000000>;

                required-opps = <&rpmhpd_opp_svs>;

            };



            opp-375000000 {

                opp-hz = /bits/ 64 <375000000>;

                required-opps = <&rpmhpd_opp_svs_l1>;

            };



            opp-500000000 {

                opp-hz = /bits/ 64 <500000000>;

                required-opps = <&rpmhpd_opp_nom>;

            };

        };

    };

...

Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml

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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8450 Display MDSS



maintainers:

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>



description:

  SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like

  DPU display controller, DSI and DP interfaces etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,sm8450-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display sf AXI

      - description: Display core



  iommus:

    maxItems: 1



  interconnects:

    maxItems: 2



  interconnect-names:

    maxItems: 2



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    properties:

      compatible:

        const: qcom,sm8450-dpu



  "^dsi@[0-9a-f]+$":

    type: object

    properties:

      compatible:

        const: qcom,mdss-dsi-ctrl



  "^phy@[0-9a-f]+$":

    type: object

    properties:

      compatible:

        const: qcom,dsi-phy-5nm-8450



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8450-dispcc.h>

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-subsystem@ae00000 {

        compatible = "qcom,sm8450-mdss";

        reg = <0x0ae00000 0x1000>;

        reg-names = "mdss";



        interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,

                        <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;

        interconnect-names = "mdp0-mem", "mdp1-mem";



        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;



        power-domains = <&dispcc MDSS_GDSC>;



        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

                 <&gcc GCC_DISP_HF_AXI_CLK>,

                 <&gcc GCC_DISP_SF_AXI_CLK>,

                 <&dispcc DISP_CC_MDSS_MDP_CLK>;

        clock-names = "iface", "bus", "nrt_bus", "core";



        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <1>;



        iommus = <&apps_smmu 0x2800 0x402>;



        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        display-controller@ae01000 {

            compatible = "qcom,sm8450-dpu";

            reg = <0x0ae01000 0x8f000>,

                  <0x0aeb0000 0x2008>;

            reg-names = "mdp", "vbif";



            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                    <&gcc GCC_DISP_SF_AXI_CLK>,

                    <&dispcc DISP_CC_MDSS_AHB_CLK>,

                    <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                    <&dispcc DISP_CC_MDSS_MDP_CLK>,

                    <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

            clock-names = "bus",

                          "nrt_bus",

                          "iface",

                          "lut",

                          "core",

                          "vsync";



            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

            assigned-clock-rates = <19200000>;



            operating-points-v2 = <&mdp_opp_table>;

            power-domains = <&rpmhpd SM8450_MMCX>;



            interrupt-parent = <&mdss>;

            interrupts = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;

                    dpu_intf1_out: endpoint {

                        remote-endpoint = <&dsi0_in>;

                    };

                };



                port@1 {

                    reg = <1>;

                    dpu_intf2_out: endpoint {

                        remote-endpoint = <&dsi1_in>;

                    };

                };

            };



            mdp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-172000000{

                    opp-hz = /bits/ 64 <172000000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-200000000 {

                    opp-hz = /bits/ 64 <200000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-325000000 {

                    opp-hz = /bits/ 64 <325000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-375000000 {

                    opp-hz = /bits/ 64 <375000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-500000000 {

                    opp-hz = /bits/ 64 <500000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

            };

        };



        dsi@ae94000 {

            compatible = "qcom,mdss-dsi-ctrl";

            reg = <0x0ae94000 0x400>;

            reg-names = "dsi_ctrl";



            interrupt-parent = <&mdss>;

            interrupts = <4>;



            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,

                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,

                     <&dispcc DISP_CC_MDSS_AHB_CLK>,

                     <&gcc GCC_DISP_HF_AXI_CLK>;

            clock-names = "byte",

                          "byte_intf",

                          "pixel",

                          "core",

                          "iface",

                          "bus";



            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,

                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;

            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;



            operating-points-v2 = <&dsi_opp_table>;

            power-domains = <&rpmhpd SM8450_MMCX>;



            phys = <&dsi0_phy>;

            phy-names = "dsi";



            #address-cells = <1>;

            #size-cells = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;

                    dsi0_in: endpoint {

                        remote-endpoint = <&dpu_intf1_out>;

                    };

                };



                port@1 {

                    reg = <1>;

                    dsi0_out: endpoint {

                    };

                };

            };



            dsi_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-160310000{

                    opp-hz = /bits/ 64 <160310000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-187500000 {

                    opp-hz = /bits/ 64 <187500000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-300000000 {

                    opp-hz = /bits/ 64 <300000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-358000000 {

                    opp-hz = /bits/ 64 <358000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };

            };

        };



        dsi0_phy: phy@ae94400 {

            compatible = "qcom,dsi-phy-5nm-8450";

            reg = <0x0ae94400 0x200>,

                  <0x0ae94600 0x280>,

                  <0x0ae94900 0x260>;

            reg-names = "dsi_phy",

                        "dsi_phy_lane",

                        "dsi_pll";



            #clock-cells = <1>;

            #phy-cells = <0>;



            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

                     <&rpmhcc RPMH_CXO_CLK>;

            clock-names = "iface", "ref";

            vdds-supply = <&vreg_dsi_phy>;

        };



        dsi@ae96000 {

            compatible = "qcom,mdss-dsi-ctrl";

            reg = <0x0ae96000 0x400>;

            reg-names = "dsi_ctrl";



            interrupt-parent = <&mdss>;

            interrupts = <5>;



            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,

                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,

                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,

                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,

                     <&dispcc DISP_CC_MDSS_AHB_CLK>,

                     <&gcc GCC_DISP_HF_AXI_CLK>;

            clock-names = "byte",

                          "byte_intf",

                          "pixel",

                          "core",

                          "iface",

                          "bus";



            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,

                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;

            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;



            operating-points-v2 = <&dsi_opp_table>;

            power-domains = <&rpmhpd SM8450_MMCX>;



            phys = <&dsi1_phy>;

            phy-names = "dsi";



            #address-cells = <1>;

            #size-cells = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;

                    dsi1_in: endpoint {

                        remote-endpoint = <&dpu_intf2_out>;

                    };

                };



                port@1 {

                    reg = <1>;

                    dsi1_out: endpoint {

                    };

                };

            };

        };



        dsi1_phy: phy@ae96400 {

            compatible = "qcom,dsi-phy-5nm-8450";

            reg = <0x0ae96400 0x200>,

                  <0x0ae96600 0x280>,

                  <0x0ae96900 0x260>;

            reg-names = "dsi_phy",

                        "dsi_phy_lane",

                        "dsi_pll";



            #clock-cells = <1>;

            #phy-cells = <0>;



            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

                     <&rpmhcc RPMH_CXO_CLK>;

            clock-names = "iface", "ref";

            vdds-supply = <&vreg_dsi_phy>;

        };

    };

...