Commit db11c0a7 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by PvsNarasimha
Browse files

iommu/amd: Use msi_msg shadow structs 

mainline inclusion
from mainline-v5.11-rc1
commit b5c3786e
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAU6ZD

Reference: https://github.com/torvalds/linux/commit/b5c3786ee3704bd8cd5b29ae168526f2b1af4557



--------------------------------

commit b5c3786e upstream

Get rid of the macro mess and use the shadow structs for the x86 specific
MSI message format. Convert the intcapxt setup to use named bitfields as
well while touching it anyway.

[Backport changes]

1. In "drivers/iommu/amd/init.c" file, in "iommu_update_intcapxt()" the
x2apic_enabled() check and "val" variable assignment got removed
as per upstream commit.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201024213535.443185-15-dwmw2@infradead.org


Signed-off-by: default avatarPvsNarasimha <PVS.NarasimhaRao@amd.com>
parent b1d911f3

drivers/iommu/amd/init.c

+26 −20
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ 
#include <asm/pci-direct.h>

#include <asm/iommu.h>

#include <asm/apic.h>

#include <asm/msidef.h>

#include <asm/gart.h>

#include <asm/x86_init.h>

#include <asm/iommu_table.h>
@@ -2021,10 +2020,16 @@ static int iommu_setup_msi(struct amd_iommu *iommu) 
	return 0;

}



#define XT_INT_DEST_MODE(x)	(((x) & 0x1ULL) << 2)

#define XT_INT_DEST_LO(x)	(((x) & 0xFFFFFFULL) << 8)

#define XT_INT_VEC(x)		(((x) & 0xFFULL) << 32)

#define XT_INT_DEST_HI(x)	((((x) >> 24) & 0xFFULL) << 56)

union intcapxt {

	u64	capxt;

	u64	reserved_0		:  2,

		dest_mode_logical	:  1,

		reserved_1		:  5,

		destid_0_23		: 24,

		vector			:  8,

		reserved_2		: 16,

		destid_24_31		:  8;

} __attribute__ ((packed));



/*

 * Setup the IntCapXT registers with interrupt routing information
@@ -2033,28 +2038,29 @@ static int iommu_setup_msi(struct amd_iommu *iommu) 
 */

static void iommu_update_intcapxt(struct amd_iommu *iommu)

{

	u64 val;

	u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET);

	u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET);

	u32 data    = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET);

	bool dm     = (addr_lo >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;

	u32 dest    = ((addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xFF);

	struct msi_msg msg;

	union intcapxt xt;

	u32 destid;



	msg.address_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET);

	msg.address_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET);

	msg.data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET);



	if (x2apic_enabled())

		dest |= MSI_ADDR_EXT_DEST_ID(addr_hi);

	destid = x86_msi_msg_get_destid(&msg, x2apic_enabled());



	val = XT_INT_VEC(data & 0xFF) |

	      XT_INT_DEST_MODE(dm) |

	      XT_INT_DEST_LO(dest) |

	      XT_INT_DEST_HI(dest);

	xt.capxt = 0ULL;

	xt.dest_mode_logical = msg.arch_data.dest_mode_logical;

	xt.vector = msg.arch_data.vector;

	xt.destid_0_23 = destid & GENMASK(23, 0);

	xt.destid_24_31 = destid >> 24;



	/**

	 * Current IOMMU implemtation uses the same IRQ for all

	 * 3 IOMMU interrupts.

	 */

	writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);

	writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET);

	writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET);

	writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);

	writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET);

	writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET);

}



static void _irq_notifier_notify(struct irq_affinity_notify *notify,

drivers/iommu/amd/iommu.c

+9 −5
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#include <asm/io_apic.h>

#include <asm/apic.h>

#include <asm/hw_irq.h>

#include <asm/msidef.h>

#include <asm/proto.h>

#include <asm/iommu.h>

#include <asm/gart.h>
@@ -3665,13 +3664,20 @@ struct irq_remap_ops amd_iommu_irq_ops = { 
	.get_irq_domain		= get_irq_domain,

};



static void fill_msi_msg(struct msi_msg *msg, u32 index)

{

	msg->data = index;

	msg->address_lo = 0;

	msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;

	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;

}



static void irq_remapping_prepare_irte(struct amd_ir_data *data,

				       struct irq_cfg *irq_cfg,

				       struct irq_alloc_info *info,

				       int devid, int index, int sub_handle)

{

	struct irq_2_irte *irte_info = &data->irq_2_irte;

	struct msi_msg *msg = &data->msi_entry;

	struct IO_APIC_route_entry *entry;

	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
@@ -3702,9 +3708,7 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data, 
	case X86_IRQ_ALLOC_TYPE_HPET:

	case X86_IRQ_ALLOC_TYPE_PCI_MSI:

	case X86_IRQ_ALLOC_TYPE_PCI_MSIX:

		msg->address_hi = MSI_ADDR_BASE_HI;

		msg->address_lo = MSI_ADDR_BASE_LO;

		msg->data = irte_info->index;

		fill_msi_msg(&data->msi_entry, irte_info->index);

		break;



	default: