Commit b1d911f3 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by PvsNarasimha
Browse files

iommu/intel: Use msi_msg shadow structs 

mainline inclusion
from mainline-v5.11-rc1
commit 5c0d0e2c
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAU6ZD

Reference: https://github.com/torvalds/linux/commit/5c0d0e2cc6e0e7a96c25351fd67c775e7b1f11f0



--------------------------------

commit 5c0d0e2c upstream

Use the bitfields in the x86 shadow struct to compose the MSI message.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201024213535.443185-14-dwmw2@infradead.org


Signed-off-by: default avatarPvsNarasimha <PVS.NarasimhaRao@amd.com>
parent 941edc2e

drivers/iommu/intel/irq_remapping.c

+16 −8
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ 
#include <asm/cpu.h>

#include <asm/irq_remapping.h>

#include <asm/pci-direct.h>

#include <asm/msidef.h>



#include "../irq_remapping.h"
@@ -1267,6 +1266,21 @@ static struct irq_chip intel_ir_chip = { 
	.irq_set_vcpu_affinity	= intel_ir_set_vcpu_affinity,

};



static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)

{

	memset(msg, 0, sizeof(*msg));



	msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;

	msg->arch_addr_lo.dmar_subhandle_valid = true;

	msg->arch_addr_lo.dmar_format = true;

	msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;

	msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);



	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;



	msg->arch_data.dmar_subhandle = subhandle;

}



static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,

					     struct irq_cfg *irq_cfg,

					     struct irq_alloc_info *info,
@@ -1274,7 +1288,6 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, 
{

	struct IR_IO_APIC_route_entry *entry;

	struct irte *irte = &data->irte_entry;

	struct msi_msg *msg = &data->msi_entry;



	prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);

	switch (info->type) {
@@ -1315,12 +1328,7 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, 
		else

			set_msi_sid(irte, msi_desc_to_pci_dev(info->desc));



		msg->address_hi = MSI_ADDR_BASE_HI;

		msg->data = sub_handle;

		msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |

				  MSI_ADDR_IR_SHV |

				  MSI_ADDR_IR_INDEX1(index) |

				  MSI_ADDR_IR_INDEX2(index);

		fill_msi_msg(&data->msi_entry, index, sub_handle);

		break;



	default: