Loading .mailmap +1 −0 Original line number Diff line number Diff line Loading @@ -416,6 +416,7 @@ TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org> TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn> Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com> Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws> Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com> Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Uwe Kleine-König <ukleinek@strlen.de> Loading CREDITS +9 −0 Original line number Diff line number Diff line Loading @@ -918,6 +918,11 @@ S: Ottawa, Ontario S: K1N 6Z9 S: CANADA N: Vivien Didelot E: vivien.didelot@gmail.com D: DSA framework and MV88E6XXX driver S: Montreal, Quebec, Canada N: Jeff Dike E: jdike@karaya.com W: http://user-mode-linux.sourceforge.net Loading Loading @@ -2447,6 +2452,10 @@ S: 482 Shadowgraph Dr. S: San Jose, CA 95110 S: USA N: Michal Marek E: michal.lkml@markovi.net D: Kbuild Maintainer 2009-2017 N: Martin Mares E: mj@ucw.cz W: http://www.ucw.cz/~mj/ Loading Documentation/arm64/booting.rst +8 −0 Original line number Diff line number Diff line Loading @@ -340,6 +340,14 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64) - If EL3 is present: Loading Documentation/arm64/cpu-feature-registers.rst +37 −1 Original line number Diff line number Diff line Loading @@ -92,7 +92,7 @@ operation if the source belongs to the supported system register space. The infrastructure emulates only the following system register space:: Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7 (See Table C5-6 'System instruction encodings for non-Debug System register accesses' in ARMv8 ARM DDI 0487A.h, for the list of Loading Loading @@ -293,6 +293,42 @@ infrastructure: | WFXT | [3-0] | y | +------------------------------+---------+---------+ 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | FPDP | [11-8] | y | +------------------------------+---------+---------+ 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | SIMDFMAC | [31-28] | y | +------------------------------+---------+---------+ | SIMDSP | [19-16] | y | +------------------------------+---------+---------+ | SIMDInt | [15-12] | y | +------------------------------+---------+---------+ | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | CRC32 | [19-16] | y | +------------------------------+---------+---------+ | SHA2 | [15-12] | y | +------------------------------+---------+---------+ | SHA1 | [11-8] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ Appendix I: Example ------------------- Loading Documentation/dev-tools/kmsan.rst +1 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ uninitialized in the local variable, as well as the stack where the value was copied to another memory location before use. A use of uninitialized value ``v`` is reported by KMSAN in the following cases: - in a condition, e.g. ``if (v) { ... }``; - in an indexing or pointer dereferencing, e.g. ``array[v]`` or ``*v``; - when it is copied to userspace or hardware, e.g. ``copy_to_user(..., &v, ...)``; Loading Loading
.mailmap +1 −0 Original line number Diff line number Diff line Loading @@ -416,6 +416,7 @@ TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org> TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn> Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com> Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws> Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com> Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Uwe Kleine-König <ukleinek@strlen.de> Loading
CREDITS +9 −0 Original line number Diff line number Diff line Loading @@ -918,6 +918,11 @@ S: Ottawa, Ontario S: K1N 6Z9 S: CANADA N: Vivien Didelot E: vivien.didelot@gmail.com D: DSA framework and MV88E6XXX driver S: Montreal, Quebec, Canada N: Jeff Dike E: jdike@karaya.com W: http://user-mode-linux.sourceforge.net Loading Loading @@ -2447,6 +2452,10 @@ S: 482 Shadowgraph Dr. S: San Jose, CA 95110 S: USA N: Michal Marek E: michal.lkml@markovi.net D: Kbuild Maintainer 2009-2017 N: Martin Mares E: mj@ucw.cz W: http://www.ucw.cz/~mj/ Loading
Documentation/arm64/booting.rst +8 −0 Original line number Diff line number Diff line Loading @@ -340,6 +340,14 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64) - If EL3 is present: Loading
Documentation/arm64/cpu-feature-registers.rst +37 −1 Original line number Diff line number Diff line Loading @@ -92,7 +92,7 @@ operation if the source belongs to the supported system register space. The infrastructure emulates only the following system register space:: Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7 (See Table C5-6 'System instruction encodings for non-Debug System register accesses' in ARMv8 ARM DDI 0487A.h, for the list of Loading Loading @@ -293,6 +293,42 @@ infrastructure: | WFXT | [3-0] | y | +------------------------------+---------+---------+ 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | FPDP | [11-8] | y | +------------------------------+---------+---------+ 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | SIMDFMAC | [31-28] | y | +------------------------------+---------+---------+ | SIMDSP | [19-16] | y | +------------------------------+---------+---------+ | SIMDInt | [15-12] | y | +------------------------------+---------+---------+ | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | CRC32 | [19-16] | y | +------------------------------+---------+---------+ | SHA2 | [15-12] | y | +------------------------------+---------+---------+ | SHA1 | [11-8] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ Appendix I: Example ------------------- Loading
Documentation/dev-tools/kmsan.rst +1 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ uninitialized in the local variable, as well as the stack where the value was copied to another memory location before use. A use of uninitialized value ``v`` is reported by KMSAN in the following cases: - in a condition, e.g. ``if (v) { ... }``; - in an indexing or pointer dereferencing, e.g. ``array[v]`` or ``*v``; - when it is copied to userspace or hardware, e.g. ``copy_to_user(..., &v, ...)``; Loading