Commit d8e0f976 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "This is quite a quiet release but some new drivers mean that the
  diffstat is fairly large. The new drivers include the aspeed driver
  which is migrated from MTD as part of the ongoing move of controllers
  with specialised support for SPI flashes into the SPI subsystem.

   - Support for devices which flip CPHA during recieve only transfers
     (eg, if MOSI and MISO have inverted polarity).

   - Overhaul of the i.MX driver, including the addition of PIO support
     for better performance on small transfers.

   - Migration of the Aspeed driver from MTD.

   - Support for Aspeed AST2400, Ingenic JZ4775 and X1/2000 and MediaTek
     IPM and SFI"

* tag 'spi-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (84 commits)
  spi: spi-au1550: replace ternary operator with min()
  mtd: spi-nor: aspeed: set the decoding size to at least 2MB for AST2600
  spi: aspeed: Calibrate read timings
  spi: aspeed: Add support for the AST2400 SPI controller
  spi: aspeed: Workaround AST2500 limitations
  spi: aspeed: Adjust direct mapping to device size
  spi: aspeed: Add support for direct mapping
  spi: spi-mem: Convert Aspeed SMC driver to spi-mem
  spi: Convert the Aspeed SMC controllers device tree binding
  spi: spi-cadence: Update ISR status variable type to irqreturn_t
  spi: Doc fix - Describe add_lock and dma_map_dev in spi_controller
  spi: cadence-quadspi: Handle spi_unregister_master() in remove()
  spi: stm32-qspi: Remove SR_BUSY bit check before sending command
  spi: stm32-qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd()
  spi: stm32-qspi: Fix wait_cmd timeout in APM mode
  spi: cadence-quadspi: remove unnecessary (void *) casts
  spi: cadence-quadspi: Add missing blank line in cqspi_request_mmap_dma()
  spi: spi-imx: mx51_ecspi_prepare_message(): skip writing MX51_ECSPI_CONFIG register if unchanged
  spi: spi-imx: add PIO polling support
  spi: spi-imx: replace struct spi_imx_data::bitbang by pointer to struct spi_controller
  ...
parents 9b18d07b 9c63b846

Documentation/devicetree/bindings/mtd/aspeed-smc.txt

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* Aspeed Firmware Memory controller

* Aspeed SPI Flash Memory Controller



The Firmware Memory Controller in the Aspeed AST2500 SoC supports

three chip selects, two of which are always of SPI type and the third

can be SPI or NOR type flash. These bindings only describe SPI.



The two SPI flash memory controllers in the AST2500 each support two

chip selects.



Required properties:

  - compatible : Should be one of

	"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller

	"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller

	"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller

	"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers



  - reg : the first contains the control register location and length,

          the second contains the memory window mapping address and length

  - #address-cells : must be 1 corresponding to chip select child binding

  - #size-cells : must be 0 corresponding to chip select child binding



Optional properties:

  - interrupts : Should contain the interrupt for the dma device if an

    FMC



The child nodes are the SPI flash modules which must have a compatible

property as specified in bindings/mtd/jedec,spi-nor.txt



Optionally, the child node can contain properties for SPI mode (may be

ignored):

  - spi-max-frequency - max frequency of spi bus





Example:

fmc: fmc@1e620000 {

	compatible = "aspeed,ast2500-fmc";

	reg = < 0x1e620000 0x94

		0x20000000 0x02000000 >;

	#address-cells = <1>;

	#size-cells = <0>;

	interrupts = <19>;

	flash@0 {

		reg = < 0 >;

		compatible = "jedec,spi-nor";

		/* spi-max-frequency = <>; */

		/* m25p,fast-read; */

		#address-cells = <1>;

		#size-cells = <1>;

	};

};

Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Aspeed SMC controllers bindings



maintainers:

  - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

  - Cédric Le Goater <clg@kaod.org>



description: |

  This binding describes the Aspeed Static Memory Controllers (FMC and

  SPI) of the AST2400, AST2500 and AST2600 SOCs.



allOf:

  - $ref: "spi-controller.yaml#"



properties:

  compatible:

    enum:

      - aspeed,ast2600-fmc

      - aspeed,ast2600-spi

      - aspeed,ast2500-fmc

      - aspeed,ast2500-spi

      - aspeed,ast2400-fmc

      - aspeed,ast2400-spi



  reg:

    items:

      - description: registers

      - description: memory mapping



  clocks:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>

    #include <dt-bindings/clock/ast2600-clock.h>



    spi@1e620000 {

        reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;

        #address-cells = <1>;

        #size-cells = <0>;

        compatible = "aspeed,ast2600-fmc";

        clocks = <&syscon ASPEED_CLK_AHB>;

        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;



        flash@0 {

                reg = < 0 >;

                compatible = "jedec,spi-nor";

                spi-max-frequency = <50000000>;

                spi-rx-bus-width = <2>;

        };



        flash@1 {

                reg = < 1 >;

                compatible = "jedec,spi-nor";

                spi-max-frequency = <50000000>;

                spi-rx-bus-width = <2>;

        };



        flash@2 {

                reg = < 2 >;

                compatible = "jedec,spi-nor";

                spi-max-frequency = <50000000>;

                spi-rx-bus-width = <2>;

        };

    };

Documentation/devicetree/bindings/spi/ingenic,spi.yaml

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@@ -18,7 +18,10 @@ properties: 
    oneOf:

      - enum:

          - ingenic,jz4750-spi

          - ingenic,jz4775-spi

          - ingenic,jz4780-spi

          - ingenic,x1000-spi

          - ingenic,x2000-spi

      - items:

          - enum:

              - ingenic,jz4760-spi

Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml

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@@ -53,16 +53,20 @@ properties: 
    maxItems: 1



  clocks:

    minItems: 3

    items:

      - description: clock used for the parent clock

      - description: clock used for the muxes clock

      - description: clock used for the clock gate

      - description: clock used for the AHB bus, this clock is optional



  clock-names:

    minItems: 3

    items:

      - const: parent-clk

      - const: sel-clk

      - const: spi-clk

      - const: hclk



  mediatek,pad-select:

    $ref: /schemas/types.yaml#/definitions/uint32-array

Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SPI-NAND flash controller for MediaTek ARM SoCs



maintainers:

  - Chuanhong Guo <gch981213@gmail.com>



description: |

  The Mediatek SPI-NAND flash controller is an extended version of

  the Mediatek NAND flash controller. It can perform standard SPI

  instructions with one continuous write and one read for up-to 0xa0

  bytes. It also supports typical SPI-NAND page cache operations

  in single, dual or quad IO mode with pipelined ECC encoding/decoding

  using the accompanying ECC engine. There should be only one spi

  slave device following generic spi bindings.



allOf:

  - $ref: /schemas/spi/spi-controller.yaml#



properties:

  compatible:

    enum:

      - mediatek,mt7622-snand

      - mediatek,mt7629-snand



  reg:

    items:

      - description: core registers



  interrupts:

    items:

      - description: NFI interrupt



  clocks:

    items:

      - description: clock used for the controller

      - description: clock used for the SPI bus



  clock-names:

    items:

      - const: nfi_clk

      - const: pad_clk



  nand-ecc-engine:

    description: device-tree node of the accompanying ECC engine.

    $ref: /schemas/types.yaml#/definitions/phandle



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - nand-ecc-engine



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/mt7622-clk.h>

    soc {

      #address-cells = <2>;

      #size-cells = <2>;

      snfi: spi@1100d000 {

        compatible = "mediatek,mt7622-snand";

        reg = <0 0x1100d000 0 0x1000>;

        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;

        clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;

        clock-names = "nfi_clk", "pad_clk";

        nand-ecc-engine = <&bch>;

        #address-cells = <1>;

        #size-cells = <0>;



        flash@0 {

          compatible = "spi-nand";

          reg = <0>;

          spi-tx-bus-width = <4>;

          spi-rx-bus-width = <4>;

          nand-ecc-engine = <&snfi>;

        };

      };

    };