Unverified Commit d8da829a authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!2541 Intel: Backport some SPR and EMR PMU related upstream bugfixes to OLK-5.10 

Merge Pull Request from: @yunyingsun 
 
Title: Backport some SPR and EMR PMU related upstream bugfixes to OLK-5.10

Content:
There're some PMU related upstream bugfixes that are needed for SPR and EMR:
(v6.1-rc4) 0916886b perf/x86/intel: Fix pebs event constraints for SPR
(v6.4-rc4) 38776cc4 perf/x86/uncore: Correct the number of CHAs on SPR
(v6.6-rc1) 6f7f984f perf/x86/uncore: Correct the number of CHAs on EMR

They corrected the number of CHAs on SPR and EMR, also updated the PEBS event constraints for SPR.
The 3 backported patches are identical in code changes comparing to the original commit.

Intel-kernel issue:
#I8AR40:Backport some SPR and EMR PMU related upstream bugfixes to OLK-5.10

Test:
Without these backported patches, the number of "/sys/devices/uncore_cha_*" devices on SPR and EMR is wrong.
For example, with kernel that has included 38776cc4 but not having 6f7f984f, there's no /sys/devices/uncore_cha_* devices on EMR.

With these applied, the number of uncore_cha_* devices will be correct for SPR and EMR.

Known issue:
N/A

Default config change:
N/A
 
 
Link:https://gitee.com/openeuler/kernel/pulls/2541

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 69c2f248 f9835c88

arch/x86/events/intel/ds.c

+7 −2
Original line number Diff line number Diff line
@@ -947,8 +947,13 @@ struct event_constraint intel_spr_pebs_event_constraints[] = { 
	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),

	INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),

	INTEL_PSD_CONSTRAINT(0x2cd, 0x1),

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x2d0, 0xf),

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),	/* MEM_INST_RETIRED.LOCK_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),	/* MEM_INST_RETIRED.ALL_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),	/* MEM_INST_RETIRED.ALL_STORES */



	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),

arch/x86/events/intel/uncore_snbep.c

+21 −0
Original line number Diff line number Diff line
@@ -5629,6 +5629,7 @@ static struct intel_uncore_type spr_uncore_mdf = { 
};



#define UNCORE_SPR_NUM_UNCORE_TYPES		12

#define UNCORE_SPR_CHA				0

#define UNCORE_SPR_IIO				1

#define UNCORE_SPR_IMC				6

#define UNCORE_SPR_UPI				8
@@ -5926,12 +5927,32 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types, 
	return max + 1;

}



#define SPR_MSR_UNC_CBO_CONFIG		0x2FFE



void spr_uncore_cpu_init(void)

{

	struct intel_uncore_type *type;

	u64 num_cbo;



	uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,

						UNCORE_SPR_MSR_EXTRA_UNCORES,

						spr_msr_uncores);



	type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);

	if (type) {

		/*

		 * The value from the discovery table (stored in the type->num_boxes

		 * of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a

		 * firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it.

		 */

		rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);

		/*

		 * The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact

		 * the EMR XCC. Don't let the value from the MSR replace the existing value.

		 */

		if (num_cbo)

			type->num_boxes = num_cbo;

	}

	spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);

}