Commit d85b82f0 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a07g044: Add GPIO clock and reset entries 



Add GPIO clock and reset entries in CPG driver.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210712194422.12405-4-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d520af34

drivers/clk/renesas/r9a07g044-cpg.c

+5 −0
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x584, 4),

	DEF_MOD("sci0",		R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,

				0x588, 0),

	DEF_MOD("gpio",		R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,

				0x598, 0),

};



static struct rzg2l_reset r9a07g044_resets[] = {
@@ -166,6 +168,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),

	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),

	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),

	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),

	DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),

	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),

};



static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {