Commit d520af34 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries 



Add SSIF-2 clock and reset entries in CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210702135010.5937-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 03fa6e4b

drivers/clk/renesas/r9a07g044-cpg.c

+20 −0
Original line number Diff line number Diff line
@@ -96,6 +96,22 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x52c, 0),

	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,

				0x52c, 1),

	DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,

				0x570, 0),

	DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,

				0x570, 1),

	DEF_MOD("ssi1_pclk",	R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,

				0x570, 2),

	DEF_MOD("ssi1_sfr",	R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,

				0x570, 3),

	DEF_MOD("ssi2_pclk",	R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,

				0x570, 4),

	DEF_MOD("ssi2_sfr",	R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,

				0x570, 5),

	DEF_MOD("ssi3_pclk",	R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,

				0x570, 6),

	DEF_MOD("ssi3_sfr",	R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,

				0x570, 7),

	DEF_MOD("usb0_host",	R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,

				0x578, 0),

	DEF_MOD("usb1_host",	R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
@@ -132,6 +148,10 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),

	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),

	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),

	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),

	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),

	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),

	DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),

	DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),

	DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),

	DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),