Commit d73ee753 authored by Pratyush Yadav's avatar Pratyush Yadav Committed by Vignesh Raghavendra
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mtd: spi-nor: core: perform a Soft Reset on shutdown 



Perform a Soft Reset on shutdown on flashes that support it so that the
flash can be reset to its initial state and any configurations made by
spi-nor (given that they're only done in volatile registers) will be
reset. This will hand back the flash in pristine state for any further
operations on it.

Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20201005153138.6437-13-p.yadav@ti.com
parent 1131324a

drivers/mtd/spi-nor/core.c

+45 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ 


#define SPI_NOR_MAX_ADDR_WIDTH	4



#define SPI_NOR_SRST_SLEEP_MIN 200

#define SPI_NOR_SRST_SLEEP_MAX 400



/**

 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the

 *			   extension type.
@@ -3174,6 +3177,45 @@ static int spi_nor_init(struct spi_nor *nor) 
	return 0;

}



static void spi_nor_soft_reset(struct spi_nor *nor)

{

	struct spi_mem_op op;

	int ret;



	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),

			SPI_MEM_OP_NO_DUMMY,

			SPI_MEM_OP_NO_ADDR,

			SPI_MEM_OP_NO_DATA);



	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);



	ret = spi_mem_exec_op(nor->spimem, &op);

	if (ret) {

		dev_warn(nor->dev, "Software reset failed: %d\n", ret);

		return;

	}



	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),

			SPI_MEM_OP_NO_DUMMY,

			SPI_MEM_OP_NO_ADDR,

			SPI_MEM_OP_NO_DATA);



	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);



	ret = spi_mem_exec_op(nor->spimem, &op);

	if (ret) {

		dev_warn(nor->dev, "Software reset failed: %d\n", ret);

		return;

	}



	/*

	 * Software Reset is not instant, and the delay varies from flash to

	 * flash. Looking at a few flashes, most range somewhere below 100

	 * microseconds. So, sleep for a range of 200-400 us.

	 */

	usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);

}



/* mtd resume handler */

static void spi_nor_resume(struct mtd_info *mtd)

{
@@ -3193,6 +3235,9 @@ void spi_nor_restore(struct spi_nor *nor) 
	if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&

	    nor->flags & SNOR_F_BROKEN_RESET)

		nor->params->set_4byte_addr_mode(nor, false);



	if (nor->flags & SNOR_F_SOFT_RESET)

		spi_nor_soft_reset(nor);

}

EXPORT_SYMBOL_GPL(spi_nor_restore);

include/linux/mtd/spi-nor.h

+2 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ 
#define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */

#define SPINOR_OP_RDEAR		0xc8	/* Read Extended Address Register */

#define SPINOR_OP_WREAR		0xc5	/* Write Extended Address Register */

#define SPINOR_OP_SRSTEN	0x66	/* Software Reset Enable */

#define SPINOR_OP_SRST		0x99	/* Software Reset */



/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */

#define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */