Commit 1131324a authored by Pratyush Yadav's avatar Pratyush Yadav Committed by Vignesh Raghavendra
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mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT



A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.

Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20201005153138.6437-12-p.yadav@ti.com
parent a33c89db
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+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ enum spi_nor_option_flags {
	SNOR_F_HAS_4BIT_BP      = BIT(12),
	SNOR_F_HAS_SR_BP3_BIT6  = BIT(13),
	SNOR_F_IO_MODE_EN_VOLATILE = BIT(14),
	SNOR_F_SOFT_RESET	= BIT(15),
};

struct spi_nor_read_command {
+4 −0
Original line number Diff line number Diff line
@@ -608,6 +608,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
		break;
	}

	/* Soft Reset support. */
	if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SWRST_EN_RST)
		nor->flags |= SNOR_F_SOFT_RESET;

	/* Stop here if not JESD216 rev C or later. */
	if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
		return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ struct sfdp_bfpt {
#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD		(0x4UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1		(0x5UL << 20) /* Spansion */

#define BFPT_DWORD16_SWRST_EN_RST		BIT(12)

#define BFPT_DWORD18_CMD_EXT_MASK		GENMASK(30, 29)
#define BFPT_DWORD18_CMD_EXT_REP		(0x0UL << 29) /* Repeat */
#define BFPT_DWORD18_CMD_EXT_INV		(0x1UL << 29) /* Invert */