Commit d6ffef26 authored by Jia He's avatar Jia He
Browse files

arm64: errata: Expand speculative SSBS workaround 

mainline inclusion
from mainline-v6.11-rc1
commit 75b3c43eab594bfbd8184ec8ee1a6b820950819a
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB3K2H
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=75b3c43eab59

------------------------------------

[ Upstream commit 75b3c43eab594bfbd8184ec8ee1a6b820950819a ]

A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS
special-purpose register does not affect subsequent speculative
instructions, permitting speculative store bypassing for a window of
time.

We worked around this for Cortex-X4 and Neoverse-V3, in commit:

  7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417")

... as per their Software Developer Errata Notice (SDEN) documents:

* Cortex-X4 SDEN v8.0, erratum 3194386:
  https://developer.arm.com/documentation/SDEN-2432808/0800/

* Neoverse-V3 SDEN v6.0, erratum 3312417:
  https://developer.arm.com/documentation/SDEN-2891958/0600/

Since then, similar errata have been published for a number of other Arm Ltd
CPUs, for which the mitigation is the same. This is described in their
respective SDEN documents:

* Cortex-A710 SDEN v19.0, errataum 3324338
  https://developer.arm.com/documentation/SDEN-1775101/1900/?lang=en

* Cortex-A720 SDEN v11.0, erratum 3456091
  https://developer.arm.com/documentation/SDEN-2439421/1100/?lang=en

* Cortex-X2 SDEN v19.0, erratum 3324338
  https://developer.arm.com/documentation/SDEN-1775100/1900/?lang=en

* Cortex-X3 SDEN v14.0, erratum 3324335
  https://developer.arm.com/documentation/SDEN-2055130/1400/?lang=en

* Cortex-X925 SDEN v8.0, erratum 3324334
  https://developer.arm.com/documentation/109108/800/?lang=en

* Neoverse-N2 SDEN v17.0, erratum 3324339
  https://developer.arm.com/documentation/SDEN-1982442/1700/?lang=en

* Neoverse-V2 SDEN v9.0, erratum 3324336
  https://developer.arm.com/documentation/SDEN-2332927/900/?lang=en



Note that due to shared design lineage, some CPUs share the same erratum
number.

Add these to the existing mitigation under CONFIG_ARM64_ERRATUM_3194386.
As listing all of the erratum IDs in the runtime description would be
unwieldy, this is reduced to:

	"SSBS not fully self-synchronizing"

... matching the description of the errata in all of the SDENs.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20240603111812.1514101-6-mark.rutland@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
[ Mark: fix conflicts in silicon-errata.rst ]
Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarJia He <justin.he@arm.com>
parent e0a8788e

Documentation/arch/arm64/silicon-errata.rst

+14 −0
Original line number Diff line number Diff line
@@ -129,14 +129,24 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #3324338        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A715     | #2645198        | ARM64_ERRATUM_2645198       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A720     | #3456091        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #3324338        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X3       | #3324335        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X4       | #3194386        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X925     | #3324334        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |
@@ -149,6 +159,10 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #3324339        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V2     | #3324336        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

arch/arm64/Kconfig

+8 −1
Original line number Diff line number Diff line
@@ -1082,12 +1082,19 @@ config ARM64_ERRATUM_3117295 
	  If unsure, say Y.



config ARM64_ERRATUM_3194386

	bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"

	bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"

	default y

	help

	  This option adds the workaround for the following errata:



	  * ARM Cortex-A710 erratam 3324338

	  * ARM Cortex-A720 erratum 3456091

	  * ARM Cortex-X2 erratum 3324338

	  * ARM Cortex-X3 erratum 3324335

	  * ARM Cortex-X4 erratum 3194386

	  * ARM Cortex-X925 erratum 3324334

	  * ARM Neoverse N2 erratum 3324339

	  * ARM Neoverse V2 erratum 3324336

	  * ARM Neoverse-V3 erratum 3312417



	  On affected cores "MSR SSBS, #0" instructions may not affect

arch/arm64/kernel/cpu_errata.c

+8 −1
Original line number Diff line number Diff line
@@ -536,8 +536,15 @@ static const struct midr_range erratum_ac03_cpu_38_list[] = { 


#ifdef CONFIG_ARM64_ERRATUM_3194386

static const struct midr_range erratum_spec_ssbs_list[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),

	{}

};

#endif
@@ -858,7 +865,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_3194386

	{

		.desc = "ARM errata 3194386, 3312417",

		.desc = "SSBS not fully self-synchronizing",

		.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,

		ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),

	},