Commit e0a8788e authored by Jia He's avatar Jia He
Browse files

arm64: errata: Unify speculative SSBS errata logic 

mainline inclusion
from mainline-v6.11-rc1
commit ec768766608092087dfb5c1fc45a16a6f524dee2
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB3K2H
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ec7687666080



------------------------------------

[ Upstream commit ec768766608092087dfb5c1fc45a16a6f524dee2 ]

Cortex-X4 erratum 3194386 and Neoverse-V3 erratum 3312417 are identical,
with duplicate Kconfig text and some unsightly ifdeffery. While we try
to share code behind CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS, having
separate options results in a fair amount of boilerplate code, and this
will only get worse as we expand the set of affected CPUs.

To reduce this boilerplate, unify the two behind a common Kconfig
option. This removes the duplicate text and Kconfig logic, and removes
the need for the intermediate ARM64_WORKAROUND_SPECULATIVE_SSBS option.
The set of affected CPUs is described as a list so that this can easily
be extended.

I've used ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID) as
the common option, matching the way we use ARM64_ERRATUM_1319367 to
cover Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20240603111812.1514101-5-mark.rutland@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
[ Mark: fix conflicts, drop unneeded cpucaps.h ]
Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarJia He <justin.he@arm.com>
parent dae77969

Documentation/arch/arm64/silicon-errata.rst

+1 −1
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3312417       |

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+4 −25
Original line number Diff line number Diff line
@@ -1081,34 +1081,14 @@ config ARM64_ERRATUM_3117295 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_SSBS

	bool



config ARM64_ERRATUM_3194386

	bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"

	default y

	help

	  This option adds the workaround for ARM Cortex-X4 erratum 3194386.

	  This option adds the workaround for the following errata:



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.



	  If unsure, say Y.



config ARM64_ERRATUM_3312417

	bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	default y

	help

	  This option adds the workaround for ARM Neoverse-V3 erratum 3312417.

	  * ARM Cortex-X4 erratum 3194386

	  * ARM Neoverse-V3 erratum 3312417



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected
@@ -1122,7 +1102,6 @@ config ARM64_ERRATUM_3312417 


	  If unsure, say Y.





config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/kernel/cpu_errata.c

+2 −6
Original line number Diff line number Diff line
@@ -534,14 +534,10 @@ static const struct midr_range erratum_ac03_cpu_38_list[] = { 
};

#endif



#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS

static const struct midr_range erratum_spec_ssbs_list[] = {

#ifdef CONFIG_ARM64_ERRATUM_3194386

static const struct midr_range erratum_spec_ssbs_list[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),

#endif

#ifdef CONFIG_ARM64_ERRATUM_3312417

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),

#endif

	{}

};

#endif
@@ -860,7 +856,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.cpu_enable = cpu_clear_bf16_from_user_emulation,

	},

#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS

#ifdef CONFIG_ARM64_ERRATUM_3194386

	{

		.desc = "ARM errata 3194386, 3312417",

		.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,

arch/arm64/kernel/proton-pack.c

+1 −1
Original line number Diff line number Diff line
@@ -567,7 +567,7 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) 
	 * Mitigate this with an unconditional speculation barrier, as CPUs

	 * could mis-speculate branches and bypass a conditional barrier.

	 */

	if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS))

	if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386))

		spec_bar();



	return SPECTRE_MITIGATED;