Commit d6cf886f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2023-01-19' of... 

Merge tag 'drm-intel-fixes-2023-01-19' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Reject display plane with height == 0 (Drew)
- re-disable RC6p on Sandy Bridge (Sasa)
- Fix hugepages' selftest (Chris)
- DG2 hw workarounds (Matt Atwood)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y8mf3/ANNWctpc7R@intel.com
parents fc70e13d afdecb23

drivers/gpu/drm/i915/display/skl_universal_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -1627,7 +1627,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) 
	u32 offset;

	int ret;



	if (w > max_width || w < min_width || h > max_height) {

	if (w > max_width || w < min_width || h > max_height || h < 1) {

		drm_dbg_kms(&dev_priv->drm,

			    "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",

			    w, h, min_width, max_width, max_height);

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

+4 −4
Original line number Diff line number Diff line
@@ -1847,7 +1847,7 @@ static int igt_shrink_thp(void *arg) 
			I915_SHRINK_ACTIVE);

	i915_vma_unpin(vma);

	if (err)

		goto out_put;

		goto out_wf;



	/*

	 * Now that the pages are *unpinned* shrinking should invoke
@@ -1863,19 +1863,19 @@ static int igt_shrink_thp(void *arg) 
		pr_err("unexpected pages mismatch, should_swap=%s\n",

		       str_yes_no(should_swap));

		err = -EINVAL;

		goto out_put;

		goto out_wf;

	}



	if (should_swap == (obj->mm.page_sizes.sg || obj->mm.page_sizes.phys)) {

		pr_err("unexpected residual page-size bits, should_swap=%s\n",

		       str_yes_no(should_swap));

		err = -EINVAL;

		goto out_put;

		goto out_wf;

	}



	err = i915_vma_pin(vma, 0, 0, flags);

	if (err)

		goto out_put;

		goto out_wf;



	while (n--) {

		err = cpu_check(obj, n, 0xdeadbeaf);

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+7 −3
Original line number Diff line number Diff line
@@ -429,9 +429,10 @@ 
#define   RC_OP_FLUSH_ENABLE			(1 << 0)

#define   HIZ_RAW_STALL_OPT_DISABLE		(1 << 2)

#define CACHE_MODE_1				_MMIO(0x7004) /* IVB+ */

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)

#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)

#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	REG_BIT(6)

#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	REG_BIT(6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	REG_BIT(1)



#define GEN7_GT_MODE				_MMIO(0x7008)

#define   GEN9_IZ_HASHING_MASK(slice)		(0x3 << ((slice) * 2))
@@ -457,6 +458,9 @@ 
#define GEN8_L3CNTLREG				_MMIO(0x7034)

#define   GEN8_ERRDETBCTRL			(1 << 9)



#define PSS_MODE2				_MMIO(0x703c)

#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)



#define GEN7_SC_INSTDONE			_MMIO(0x7100)

#define GEN12_SC_INSTDONE_EXTRA			_MMIO(0x7104)

#define GEN12_SC_INSTDONE_EXTRA2		_MMIO(0x7108)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+9 −1
Original line number Diff line number Diff line
@@ -774,8 +774,16 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 
	    IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

		wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);



	/* Wa_18018764978:dg2 */

	if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||

	    IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

		wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);



	/* Wa_15010599737:dg2 */

	wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);



	/* Wa_18019271663:dg2 */

	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);

}



static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,

drivers/gpu/drm/i915/i915_pci.c

+2 −1
Original line number Diff line number Diff line
@@ -423,7 +423,8 @@ static const struct intel_device_info ilk_m_info = { 
	.has_coherent_ggtt = true, \

	.has_llc = 1, \

	.has_rc6 = 1, \

	.has_rc6p = 1, \

	/* snb does support rc6p, but enabling it causes various issues */ \

	.has_rc6p = 0, \

	.has_rps = true, \

	.dma_mask_size = 40, \

	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \