Commit d635f6cc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-05-20' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull, amdgpu and msm make up most of these, nothing too
  serious, also one i915 and one exynos.

  I didn't get a misc fixes pull this week (one of the maintainers is
  off, so have to engage the backup) so I think there are a few
  outstanding patches that will show up next week,

  amdgpu:
   - update gfx11 clock counter logic
   - Fix a race when disabling gfxoff on gfx10/11 for profiling
   - Raven/Raven2/PCO clock counter fix
   - Add missing get_vbios_fb_size for GMC 11
   - Fix a spurious irq warning in the device remove case
   - Fix possible power mode mismatch between driver and PMFW
   - USB4 fix

  exynos:
   - fix build warning

  i915:
   - fix missing NULL check in HDCP code

  msm:
   - display:
      - msm8998: fix fetch and qos to align with downstream
      - msm8998: fix LM pairs to align with downstream
      - remove unused INTF0 interrupt mask on some chipsets
      - remove TE2 block from relevant chipsets
      - relocate non-MDP_TOP offset to different header
      - fix some indentation
      - fix register offets/masks for dither blocks
      - make ping-ping block length 0
      - remove duplicated defines
      - fix log mask for writeback block
      - unregister the hdmi codec for dp during unbind
      - fix yaml warnings
   - gpu:
      - fix submit error path leak
      - arm-smmu-qcom fix for regression that broke per-process page
        tables
      - fix no-iommu crash"

* tag 'drm-fixes-2023-05-20' of git://anongit.freedesktop.org/drm/drm: (29 commits)
  drm/amd/display: enable dpia validate
  drm/amd/pm: fix possible power mode mismatch between driver and PMFW
  drm/amdgpu: skip disabling fence driver src_irqs when device is unplugged
  drm/amdgpu/gmc11: implement get_vbios_fb_size()
  drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id
  drm/amdgpu/gfx11: Adjust gfxoff before powergating on gfx11 as well
  drm/amdgpu/gfx10: Disable gfxoff before disabling powergating.
  drm/amdgpu/gfx11: update gpu_clock_counter logic
  drm/msm: Be more shouty if per-process pgtables aren't working
  iommu/arm-smmu-qcom: Fix missing adreno_smmu's
  drm/i915/hdcp: Check if media_gt exists
  drm/exynos: fix g2d_open/close helper function definitions
  drm/msm: Fix submit error-path leaks
  drm/msm/iommu: Fix null pointer dereference in no-IOMMU case
  dt-bindings: display/msm: dsi-controller-main: Document qcom, master-dsi and qcom, sync-dual-dsi
  drm/msm/dpu: Remove duplicate register defines from INTF
  drm/msm/dpu: Set PINGPONG block length to zero for DPU >= 7.0.0
  drm/msm/dpu: Use V2 DITHER PINGPONG sub-block in SM8[34]50/SC8280XP
  drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typo
  drm/msm/dpu: Reindent REV_7xxx interrupt masks with tabs
  ...
parents 5565ec4e 79ef1c9d

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+12 −0
Original line number Diff line number Diff line
@@ -82,6 +82,18 @@ properties: 
      Indicates if the DSI controller is driving a panel which needs

      2 DSI links.



  qcom,master-dsi:

    type: boolean

    description: |

      Indicates if the DSI controller is the master DSI controller when

      qcom,dual-dsi-mode enabled.



  qcom,sync-dual-dsi:

    type: boolean

    description: |

      Indicates if the DSI controller needs to sync the other DSI controller

      with MIPI DCS commands when qcom,dual-dsi-mode enabled.



  assigned-clocks:

    minItems: 2

    maxItems: 4

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+2 −1
Original line number Diff line number Diff line
@@ -582,7 +582,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) 
		if (r)

			amdgpu_fence_driver_force_completion(ring);



		if (ring->fence_drv.irq_src)

		if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&

		    ring->fence_drv.irq_src)

			amdgpu_irq_put(adev, ring->fence_drv.irq_src,

				       ring->fence_drv.irq_type);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+7 −1
Original line number Diff line number Diff line
@@ -8152,8 +8152,14 @@ static int gfx_v10_0_set_powergating_state(void *handle, 
	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 6):

	case IP_VERSION(10, 3, 7):

		if (!enable)

			amdgpu_gfx_off_ctrl(adev, false);



		gfx_v10_cntl_pg(adev, enable);

		amdgpu_gfx_off_ctrl(adev, enable);



		if (enable)

			amdgpu_gfx_off_ctrl(adev, true);



		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+14 −5
Original line number Diff line number Diff line
@@ -4667,24 +4667,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
	uint64_t clock;

	uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;



	if (amdgpu_sriov_vf(adev)) {

		amdgpu_gfx_off_ctrl(adev, false);

		mutex_lock(&adev->gfx.gpu_clock_mutex);

	if (amdgpu_sriov_vf(adev)) {

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		mutex_unlock(&adev->gfx.gpu_clock_mutex);

		amdgpu_gfx_off_ctrl(adev, true);

	} else {

		preempt_disable();

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		preempt_enable();

	}

	clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);



	return clock;

}
@@ -5150,8 +5153,14 @@ static int gfx_v11_0_set_powergating_state(void *handle, 
		break;

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 4):

		if (!enable)

			amdgpu_gfx_off_ctrl(adev, false);



		gfx_v11_cntl_pg(adev, enable);

		amdgpu_gfx_off_ctrl(adev, enable);



		if (enable)

			amdgpu_gfx_off_ctrl(adev, true);



		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+14 −19
Original line number Diff line number Diff line
@@ -4003,30 +4003,25 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
		clock = clock_lo | (clock_hi << 32ULL);

		break;

	case IP_VERSION(9, 1, 0):

		preempt_disable();

		clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

		hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over

		 * roughly every 42 seconds.

		 */

		if (hi_check != clock_hi) {

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			clock_hi = hi_check;

		}

		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	case IP_VERSION(9, 2, 2):

		preempt_disable();

		if (adev->rev_id >= 0x8) {

			clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);

			hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);

		} else {

			clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		}

		/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over

		* roughly every 42 seconds.

		*/

		if (hi_check != clock_hi) {

			if (adev->rev_id >= 0x8)

				clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);

			else

				clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			clock_hi = hi_check;

		}

		preempt_enable();