Commit 79ef1c9d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.4-2023-05-18' of... 

Merge tag 'amd-drm-fixes-6.4-2023-05-18' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.4-2023-05-18:

amdgpu:
- update gfx11 clock counter logic
- Fix a race when disabling gfxoff on gfx10/11 for profiling
- Raven/Raven2/PCO clock counter fix
- Add missing get_vbios_fb_size for GMC 11
- Fix a spurious irq warning in the device remove case
- Fix possible power mode mismatch between driver and PMFW
- USB4 fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230518174811.3841-1-alexander.deucher@amd.com
parents 83ab69c9 6d600229

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+2 −1
Original line number Diff line number Diff line
@@ -582,7 +582,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) 
		if (r)

			amdgpu_fence_driver_force_completion(ring);



		if (ring->fence_drv.irq_src)

		if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&

		    ring->fence_drv.irq_src)

			amdgpu_irq_put(adev, ring->fence_drv.irq_src,

				       ring->fence_drv.irq_type);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+7 −1
Original line number Diff line number Diff line
@@ -8152,8 +8152,14 @@ static int gfx_v10_0_set_powergating_state(void *handle, 
	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 6):

	case IP_VERSION(10, 3, 7):

		if (!enable)

			amdgpu_gfx_off_ctrl(adev, false);



		gfx_v10_cntl_pg(adev, enable);

		amdgpu_gfx_off_ctrl(adev, enable);



		if (enable)

			amdgpu_gfx_off_ctrl(adev, true);



		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+14 −5
Original line number Diff line number Diff line
@@ -4667,24 +4667,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
	uint64_t clock;

	uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;



	if (amdgpu_sriov_vf(adev)) {

		amdgpu_gfx_off_ctrl(adev, false);

		mutex_lock(&adev->gfx.gpu_clock_mutex);

	if (amdgpu_sriov_vf(adev)) {

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		mutex_unlock(&adev->gfx.gpu_clock_mutex);

		amdgpu_gfx_off_ctrl(adev, true);

	} else {

		preempt_disable();

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		preempt_enable();

	}

	clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);



	return clock;

}
@@ -5150,8 +5153,14 @@ static int gfx_v11_0_set_powergating_state(void *handle, 
		break;

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 4):

		if (!enable)

			amdgpu_gfx_off_ctrl(adev, false);



		gfx_v11_cntl_pg(adev, enable);

		amdgpu_gfx_off_ctrl(adev, enable);



		if (enable)

			amdgpu_gfx_off_ctrl(adev, true);



		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+14 −19
Original line number Diff line number Diff line
@@ -4003,30 +4003,25 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
		clock = clock_lo | (clock_hi << 32ULL);

		break;

	case IP_VERSION(9, 1, 0):

		preempt_disable();

		clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

		hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over

		 * roughly every 42 seconds.

		 */

		if (hi_check != clock_hi) {

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			clock_hi = hi_check;

		}

		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	case IP_VERSION(9, 2, 2):

		preempt_disable();

		if (adev->rev_id >= 0x8) {

			clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);

			hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);

		} else {

			clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		}

		/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over

		* roughly every 42 seconds.

		*/

		if (hi_check != clock_hi) {

			if (adev->rev_id >= 0x8)

				clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);

			else

				clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			clock_hi = hi_check;

		}

		preempt_enable();

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+20 −1
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#include "umc_v8_10.h"

#include "athub/athub_3_0_0_sh_mask.h"

#include "athub/athub_3_0_0_offset.h"

#include "dcn/dcn_3_2_0_offset.h"

#include "dcn/dcn_3_2_0_sh_mask.h"

#include "oss/osssys_6_0_0_offset.h"

#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"

#include "navi10_enum.h"
@@ -546,7 +548,24 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 


static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)

{

	return 0;

	u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);

	unsigned size;



	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

		size = AMDGPU_VBIOS_VGA_ALLOCATION;

	} else {

		u32 viewport;

		u32 pitch;



		viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

		pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);

		size = (REG_GET_FIELD(viewport,

					HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *

				REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *

				4);

	}



	return size;

}



static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {