Commit d5aa4178 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx11: update gpu_clock_counter logic 



This code was written prior to previous updates to this
logic for other chips.  The RSC registers are part of
SMUIO which is an always on block so there is no need
to disable gfxoff.  Additionally add the carryover and
preemption checks.

v2: rebase

Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.y: 5591a051: drm/amdgpu: refine get gpu clock counter method
Cc: stable@vger.kernel.org # 6.2.y: 5591a051: drm/amdgpu: refine get gpu clock counter method
Cc: stable@vger.kernel.org # 6.3.y: 5591a051: drm/amdgpu: refine get gpu clock counter method
parent f1fcbaa1

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+7 −4
Original line number Diff line number Diff line
@@ -4667,24 +4667,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
	uint64_t clock;

	uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;



	if (amdgpu_sriov_vf(adev)) {

		amdgpu_gfx_off_ctrl(adev, false);

		mutex_lock(&adev->gfx.gpu_clock_mutex);

	if (amdgpu_sriov_vf(adev)) {

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		mutex_unlock(&adev->gfx.gpu_clock_mutex);

		amdgpu_gfx_off_ctrl(adev, true);

	} else {

		preempt_disable();

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		preempt_enable();

	}

	clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);



	return clock;

}