Commit 5591a051 authored by Tong Liu01's avatar Tong Liu01 Committed by Alex Deucher
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drm/amdgpu: refine get gpu clock counter method 



[why]
regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and
unaccessible under sriov.
The clock counter high bit may update during reading process.

[How]
Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with
regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sriov.
Refine get gpu clock counter method to make the result more precise.

Signed-off-by: default avatarTong Liu01 <Tong.Liu01@amd.com>
Acked-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc926fae

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+15 −2
Original line number Diff line number Diff line
@@ -4671,11 +4671,24 @@ static int gfx_v11_0_post_soft_reset(void *handle) 
static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)

{

	uint64_t clock;

	uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;



	amdgpu_gfx_off_ctrl(adev, false);

	mutex_lock(&adev->gfx.gpu_clock_mutex);

	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) |

		((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL);

	if (amdgpu_sriov_vf(adev)) {

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

	} else {

		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

		if (clock_counter_hi_pre != clock_counter_hi_after)

			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

	}

	clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);

	return clock;