Commit d5176cdb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "Nothing special, notably a lot of new Qualcomm hardware is supported,
  a RISC-V reference SoC and then some cleanups both in code and device
  tree bindings.

  Core changes:

   - Add PINCTRL_PINFUNCTION() macro and use it in several drivers

  New drivers:

   - New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on)
     pin controllers. (RISC-V.)

   - New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller

   - New subdrivers for the Qualcomm SM8550 SoC and LPASS pin
     controllers

   - New subdriver for the Qualcomm SA8775P SoC pin controller

   - New subdriver for the Qualcomm IPQ5332 SoC pin controller

   - New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin
     control

   - New subdriver for the Mediatek MT7981 SoC pin controller

  Improvements:

   - Several cleanups and refactorings to the Intel drivers

   - Add 4KOhm bias support to the Intel driver

   - Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver

   - Support general purpose clocks in the Qualcomm MSM8226 SoC

   - Several conversions to use the new I2C .probe_new() call

   - Massive clean-up of the Qualcomm Device Tree YAML schemas

   - Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC
     driver"

* tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits)
  pinctrl: qcom: Add support for i2c specific pull feature
  pinctrl: starfive: Add StarFive JH7110 aon controller driver
  pinctrl: starfive: Add StarFive JH7110 sys controller driver
  dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
  dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
  pinctrl: add mt7981 pinctrl driver
  dt-bindings: pinctrl: add bindings for MT7981 SoC
  dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated
  pinctrl: qcom: Introduce IPQ5332 TLMM driver
  dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
  dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
  pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS
  dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS
  pinctrl: at91: use devm_kasprintf() to avoid potential leaks
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples
  dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs
  dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern
  dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern
  dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example
  dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example
  ...
parents 17bbc46f 099f37a5

Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml→Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml

+15 −9
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MM IOMUX Controller

title: Freescale IMX8M IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>

  - Peng Fan <peng.fan@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
@@ -15,7 +15,11 @@ description: 


properties:

  compatible:

    const: fsl,imx8mm-iomuxc

    enum:

      - fsl,imx8mm-iomuxc

      - fsl,imx8mn-iomuxc

      - fsl,imx8mp-iomuxc

      - fsl,imx8mq-iomuxc



  reg:

    maxItems: 1
@@ -34,9 +38,10 @@ patternProperties: 
          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.

          be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>.

          The last integer CONFIG is the pad setting value like pull-up on this

          pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for

          detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:
@@ -51,7 +56,8 @@ patternProperties: 
            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.

                "pad_setting" indicates the pad configuration value to be

                applied.



    required:

      - fsl,pins

Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml

deleted100644 → 0
+0 −84
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MN IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8mn-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_reg" indicates the offset of mux register.

            - description: |

                "conf_reg" indicates the offset of pad configuration register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_val" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mn-iomuxc";

        reg = <0x30330000 0x10000>;



        pinctrl_uart2: uart2grp {

            fsl,pins =

                <0x23C 0x4A4 0x4FC 0x0 0x0	0x140>,

                <0x240 0x4A8 0x000 0x0 0x0	0x140>;

        };

    };



...

Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml

deleted100644 → 0
+0 −84
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MP IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8mp-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_reg" indicates the offset of mux register.

            - description: |

                "conf_reg" indicates the offset of pad configuration register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_val" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mp-iomuxc";

        reg = <0x30330000 0x10000>;



        pinctrl_uart2: uart2grp {

            fsl,pins =

                <0x228 0x488 0x5F0 0x0 0x6	0x49>,

                <0x228 0x488 0x000 0x0 0x0	0x49>;

        };

    };



...

Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml

deleted100644 → 0
+0 −84
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MQ IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8mq-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_reg" indicates the offset of mux register.

            - description: |

                "conf_reg" indicates the offset of pad configuration register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_val" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mq-iomuxc";

        reg = <0x30330000 0x10000>;



        pinctrl_uart1: uart1grp {

            fsl,pins =

                <0x234 0x49C 0x4F4 0x0 0x0	0x49>,

                <0x238 0x4A0 0x4F4 0x0 0x0	0x49>;

        };

    };



...

Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

+6 −6
Original line number Diff line number Diff line
@@ -70,11 +70,11 @@ allOf: 
  - $ref: "pinctrl.yaml#"



patternProperties:

  '-[0-9]+$':

  'pins$':

    type: object

    additionalProperties: false

    patternProperties:

      'pins':

      '(^pins|pins?$)':

        type: object

        additionalProperties: false

        description: |
@@ -158,7 +158,7 @@ examples: 
              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;



          i2c0_pins_a: i2c0-0 {

          i2c0_pins_a: i2c0-pins {

            pins1 {

              pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,

                <MT8135_PIN_101_SCL0__FUNC_SCL0>;
@@ -166,7 +166,7 @@ examples: 
            };

          };



          i2c1_pins_a: i2c1-0 {

          i2c1_pins_a: i2c1-pins {

            pins {

              pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,

                <MT8135_PIN_196_SCL1__FUNC_SCL1>;
@@ -174,7 +174,7 @@ examples: 
            };

          };



          i2c2_pins_a: i2c2-0 {

          i2c2_pins_a: i2c2-pins {

            pins1 {

              pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;

              bias-pull-down;
@@ -186,7 +186,7 @@ examples: 
            };

          };



          i2c3_pins_a: i2c3-0 {

          i2c3_pins_a: i2c3-pins {

            pins1 {

              pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,

                <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;