Commit d29b9924 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nva0/clk: fix accidental limiting of pll coefficients 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 75faef78

drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c

+16 −13
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, 
	 * "clk" parameter in kHz

	 * returns calculated clock

	 */

	int cv = nouveau_bios(subdev)->version.chip;

	struct nouveau_bios *bios = nouveau_bios(subdev);

	int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;

	int minM = info->vco1.min_m, maxM = info->vco1.max_m;

	int minN = info->vco1.min_n, maxN = info->vco1.max_n;
@@ -54,6 +54,8 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, 


	/* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */

	/* possibly correlated with introduction of 27MHz crystal */

	if (bios->version.major < 0x60) {

		int cv = bios->version.chip;

		if (cv < 0x17 || cv == 0x1a || cv == 0x20) {

			if (clk > 250000)

				maxM = 6;
@@ -67,6 +69,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, 
			if (clk > 340000)

				maxM = 2;

		}

	}



	P = 1 << maxP;

	if ((clk * P) < minvco) {