Loading drivers/gpu/drm/nouveau/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -93,6 +93,8 @@ nouveau-y += core/subdev/fb/ramnv44.o nouveau-y += core/subdev/fb/ramnv49.o nouveau-y += core/subdev/fb/ramnv4e.o nouveau-y += core/subdev/fb/ramnv50.o nouveau-y += core/subdev/fb/ramnva3.o nouveau-y += core/subdev/fb/ramnvaa.o nouveau-y += core/subdev/fb/ramnvc0.o nouveau-y += core/subdev/gpio/base.o nouveau-y += core/subdev/gpio/nv10.o Loading drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h +7 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,13 @@ struct nv50_fb_impl { u32 trap; }; #define nv50_ram_create(p,e,o,d) \ nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *, struct nouveau_oclass *, int, void **); int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin, u32 memtype, struct nouveau_mem **); void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **); void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *); extern int nv50_fb_memtype[0x80]; Loading drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c +1 −1 Original line number Diff line number Diff line Loading @@ -34,6 +34,6 @@ nva3_fb_oclass = &(struct nv50_fb_impl) { .fini = _nouveau_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, .base.ram = &nva3_ram_oclass, .trap = 0x000d0fff, }.base.base; drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c +1 −1 Original line number Diff line number Diff line Loading @@ -34,6 +34,6 @@ nvaa_fb_oclass = &(struct nv50_fb_impl) { .fini = _nouveau_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, .base.ram = &nvaa_ram_oclass, .trap = 0x001d07ff, }.base.base; drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c +1 −1 Original line number Diff line number Diff line Loading @@ -34,6 +34,6 @@ nvaf_fb_oclass = &(struct nv50_fb_impl) { .fini = _nouveau_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, .base.ram = &nvaa_ram_oclass, .trap = 0x089d1fff, }.base.base; Loading
drivers/gpu/drm/nouveau/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -93,6 +93,8 @@ nouveau-y += core/subdev/fb/ramnv44.o nouveau-y += core/subdev/fb/ramnv49.o nouveau-y += core/subdev/fb/ramnv4e.o nouveau-y += core/subdev/fb/ramnv50.o nouveau-y += core/subdev/fb/ramnva3.o nouveau-y += core/subdev/fb/ramnvaa.o nouveau-y += core/subdev/fb/ramnvc0.o nouveau-y += core/subdev/gpio/base.o nouveau-y += core/subdev/gpio/nv10.o Loading
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h +7 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,13 @@ struct nv50_fb_impl { u32 trap; }; #define nv50_ram_create(p,e,o,d) \ nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *, struct nouveau_oclass *, int, void **); int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin, u32 memtype, struct nouveau_mem **); void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **); void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *); extern int nv50_fb_memtype[0x80]; Loading
drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c +1 −1 Original line number Diff line number Diff line Loading @@ -34,6 +34,6 @@ nva3_fb_oclass = &(struct nv50_fb_impl) { .fini = _nouveau_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, .base.ram = &nva3_ram_oclass, .trap = 0x000d0fff, }.base.base;
drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c +1 −1 Original line number Diff line number Diff line Loading @@ -34,6 +34,6 @@ nvaa_fb_oclass = &(struct nv50_fb_impl) { .fini = _nouveau_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, .base.ram = &nvaa_ram_oclass, .trap = 0x001d07ff, }.base.base;
drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c +1 −1 Original line number Diff line number Diff line Loading @@ -34,6 +34,6 @@ nvaf_fb_oclass = &(struct nv50_fb_impl) { .fini = _nouveau_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, .base.ram = &nvaa_ram_oclass, .trap = 0x089d1fff, }.base.base;