Commit d28b1e03 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 



Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
to R9A07G044_CLK_P0_DIV2.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-5-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 98001908

drivers/clk/renesas/r9a07g044-cpg.c

+2 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A07G044_OSCCLK,

	LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,



	/* External Input Clocks */

	CLK_EXTAL,
@@ -77,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),

	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,

		dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),

	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),

	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,

		DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),