Commit 98001908 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into renesas-clk-for-v5.15 

Renesas RZ/G2L DT Binding Definitions Update

Missing definition for the P0_DIV2 core clock on the Renesas RZ/G2L
(R9A07G044) SoC, shared by driver and DT source files.
parents 1b87d5bb 0b256c40

include/dt-bindings/clock/r9a07g044-cpg.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#define R9A07G044_CLK_P2		19

#define R9A07G044_CLK_AT		20

#define R9A07G044_OSCCLK		21

#define R9A07G044_CLK_P0_DIV2		22



/* R9A07G044 Module Clocks */

#define R9A07G044_CA55_SCLK		0