Commit 0b256c40 authored Jul 19, 2021 by Lad Prabhakar Committed by Geert Uytterhoeven Jul 26, 2021

dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock

Add P0_DIV2 core clock required for CANFD module. CANFD core clock is
sourced from P0_DIV2 referenced from HW manual Rev.0.50.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-4-prabhakar.mahadev-lad.rj@bp.renesas.com

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

parent 2734d6c1

include/dt-bindings/clock/r9a07g044-cpg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@
		#define R9A07G044_CLK_P2 19
		#define R9A07G044_CLK_AT 20
		#define R9A07G044_OSCCLK 21
		#define R9A07G044_CLK_P0_DIV2 22

		/* R9A07G044 Module Clocks */
		#define R9A07G044_CA55_SCLK 0